diff options
| author | Neal Frager <neal.frager@amd.com> | 2023-02-14 13:19:59 +0000 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-03-09 13:15:00 +0100 |
| commit | 749cbcfeacd7063c83506ff5add037cd621fe451 (patch) | |
| tree | b5a0065b735ed0966fa99f86a3ed210f126bbc10 | |
| parent | cfa39857dee0fc267dcb07f4b7e39f2a1e40ccdd (diff) | |
fpga: zynqmppl: fix fpga loads command for unencrypted use case
When using the fpga loads command, the driver is passing the AES encryption
key address is all cases. However, for the authenticated, but not encrypted
use case, there is no AES encryption key, and this value is 0.
When AES encryption is not used on the fpga bitstream, the pmufw assumes that
the AES key address is a bitstream size value like what is used by the
unsecure fpga load command.
To fix the problem, this patch checks to see if the AES key address is zero.
If the AES key address is zero, it means that AES is not being used on the
bitstream and the bitstream size should be passed instead. Thus, matching
the fpga load functionality.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/fpga/zynqmppl.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index d1491da02c..7b5128fe27 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + if ((u32)(uintptr_t)fpga_sec_info->userkey_addr) + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, - (u32)(uintptr_t)fpga_sec_info->userkey_addr, - flag, ret_payload); + (u32)(uintptr_t)fpga_sec_info->userkey_addr, + flag, ret_payload); + else + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, + buf_hi, (u32)bsize, + flag, ret_payload); + if (ret) puts("PL FPGA LOAD fail\n"); else |