diff options
| author | Chanho Park <chanho61.park@samsung.com> | 2023-11-01 21:16:51 +0900 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-02 17:45:53 +0800 |
| commit | 30b0f58dc79d734684a0f1fae99179ee29fe18d3 (patch) | |
| tree | 6acfea158911f6334ac77330d66a6da6bbd160f5 | |
| parent | ebaee701a6a370b7566107d495db87ba653cc7c4 (diff) | |
riscv: dts: jh7110: Add rng device tree node
Adds jh7110 trng device tree node.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ff..13c47f7caa 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -627,6 +627,16 @@ status = "disabled"; }; + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + interrupts = <30>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; |