1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
|
/*
* Copyright (C) 2017-2021 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#define LIGHT_APCLK_ADDRBASE 0xffff011000
#define LIGHT_AONCLK_ADDRBASE 0xfffff46000
#define LIGHT_DDRCLK_ADDRBASE 0xffff005000
#define LIGHT_MISC_SUBSYS_ADDRBASE 0xfffc02d000
#define LIGHT_VI_SUBSYS_ADDRBASE 0xfff4041000
#define LIGHT_VO_SUBSYS_ADDRBASE 0xffff401000
#define LIGHT_VO_SUBSYS_R_ADDRBASE 0xffef528000
#define LIGHT_VP_SUBSYS_ADDRBASE 0xfffcc01000
#define LIGHT_DSP_SUBSYS_ADDRBASE 0xffff041000
#define LIGHT_AUDIO_SUBSYS_ADDRBASE 0xffcb000000
#define LIGHT_APSYS_RSTGEN_ADDRBASE 0xffff015000
#define LIGHT_DPU_CLOCK_GATING_CTRL0 0xffef601A28
#define LIGHT_DPU_CLOCK_GATING_CTRL1 0xffef601A2C
void show_sys_clk(void)
{
/* Do nothing for FPGA */
}
void cpu_clk_config(uint32_t cpu_freq)
{
#ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
unsigned int tmp;
/* 4. update c910_cclk to 750Mhz */
/* set cpu_pll1_foutpostdiv to 750Mhz */
writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
writel(0x01407d01, (void *)LIGHT_APCLK_ADDRBASE + 0x10);
writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
udelay(3);
writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x10));
udelay(11);
/* config bus: cpu clk ratio to 1:1 */
writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
/* switch c910_cclk to cpu_pll1_foutpostdiv */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
tmp |= 0x1;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
udelay(1);
#endif
}
void sys_clk_config(void)
{
#ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
unsigned int tmp;
/* 1. double check all pll lock */
udelay(60);
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
if (!((tmp & 0x3fe) == 0x3fe))
return;
/* 2. update sys_pll to frac mode, 2438.5536MHz */
/* switch share_sram_clk to audio_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
tmp |= 0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
/* switch audio_c906_cclk to audio_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x110);
tmp |= 0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x110);
/* switch audio_subsys_aclk to audio_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x108);
tmp |= 0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x108);
/* disable audio_i2s_src_clk */
tmp = readl((void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
tmp &= ~0x20200;
writel(tmp, (void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
/* disable peri_i2s_src_clk */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
tmp &= ~0x2;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
udelay(1);
/* set sys_pll_foutvco to 2438.5536MHz */
writel(0x20000000, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
writel(0x03606501, (void *)LIGHT_AONCLK_ADDRBASE + 0x10);
writel(0x209b3d08, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
udelay(3);
writel(0x009b3d08, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
while(!(readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90) & 0x2));
udelay(11);
/* switch share_sram_clk to sys_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
tmp &= ~0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
/* switch audio_c906_cclk to sys_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x110);
tmp &= ~0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x110);
/* swith audio_subsys_aclk to sys_pll_foutvco */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x108);
tmp &= ~0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x108);
/* 3. update audio_pll, to frac mode, 884.736MHz */
/* switch aonsys_clk to pad_osc_clk */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x100);
tmp |= 0x10;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x100);
/* set audio_pll_foutvco to frac mode, 884.736MHz */
writel(0x20000000, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
writel(0x01302401, (void *)LIGHT_AONCLK_ADDRBASE + 0x00);
writel(0x20dd2f70, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
udelay(3);
writel(0x00dd2f70, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
while(!(readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90) & 0x1));
udelay(11);
/* switch aonsys_clk to audio_pll_foutpostdiv */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x100);
tmp &= ~0x10;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x100);
/* switch aoi2c_ic_clk to audio_pll_fout3 */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x11c);
tmp &= ~0x1;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x11c);
/* enable audio_i2s_src_clk */
tmp = readl((void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
tmp |= 0x20200;
writel(tmp, (void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
/* enable peri_i2s_src_clk */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
tmp |= 0x2;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
/* set apb3_cpusys_pclk to ahb2_cpusys_hclk/2 */
/* CPU AHB 125MHz CPU pclk 125MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x130);
tmp &= ~0x8;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
udelay(1);
tmp &= ~0x7;
tmp |= 0x1;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
udelay(1);
tmp |= 0x8;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
udelay(1);
/* CPU AHB 125MHz CPU pclk 62.5MHz */
/* set ahb2_cpusys_hclk to 250Mhz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x120);
tmp |= 0x20;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
udelay(1);
tmp &= ~0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
udelay(1);
tmp &= ~0x7;
tmp |= 0x2;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
udelay(1);
tmp |= 0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
udelay(1);
tmp &= ~0x20;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
udelay(1);
/* CPU AHB 250MHz CPU pclk 125MHz */
/* perisys_apb_pclk to perisys_ahb_hclk/4 */
/* perisys_ahb_hclk 62.5MHz perisys_apb_pclk 62.5MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x150);
tmp &= ~0x8;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
udelay(1);
tmp &= ~0x7;
tmp |= 0x3;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
udelay(1);
tmp |= 0x8;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
udelay(1);
/* perisys_ahb_hclk 62.5MHz perisys_apb_pclk 15.625MHz */
/* perisys_ahb_hclk to 250MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x140);
tmp |= 0x20;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
udelay(1);
/* perisys_ahb_hclk 24MHz perisys_apb_pclk 6MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x140);
tmp &= ~0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
udelay(1);
tmp &= ~0xf;
tmp |= 0x2;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
/* perisys_ahb_hclk 24MHz perisys_apb_pclk 6MHz */
udelay(1);
tmp |= 0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
udelay(1);
tmp &= ~0x20;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
/* perisys_ahb_hclk 250MHz perisys_apb_pclk 62.5MHz */
/* set dpu0_pll_div_clk to dpu0_pll_foutpostdiv/16 as 74.25MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
tmp &= ~0x100;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
udelay(1);
tmp &= ~0xff;
tmp |= 0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
udelay(1);
tmp |= 0x100;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
udelay(1);
/* set dpu1_pll_div_clk to dpu1_pll_foutpostdiv/16 as 74.25MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
tmp &= ~0x100;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
udelay(1);
tmp &= ~0xff;
tmp |= 0x10;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
udelay(1);
tmp |= 0x100;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
udelay(1);
/*5. enable necessary gates */
/* enable dsp_subsys, vi_subsys, vo_subsys all clocls */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x220);
tmp |= 0x7;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x220);
/* AP rst_gen: VP/VO/VI/DSP */
writel(0xf, (void *)LIGHT_APSYS_RSTGEN_ADDRBASE + 0x220);
/* enable dsp0/1_cclk, dsp0/1_pclk */
tmp = readl((void *)LIGHT_DSP_SUBSYS_ADDRBASE + 0x24);
tmp |= 0xf;
writel(tmp, (void *)LIGHT_DSP_SUBSYS_ADDRBASE + 0x24);
/* enable gpu_core_clk, gpu_cfg_aclk */
tmp = readl((void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
tmp |= 0x18;
writel(tmp, (void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
tmp = readl((void *)LIGHT_VO_SUBSYS_R_ADDRBASE + 0x50);
tmp |= 0x3ff;
writel(tmp, (void *)LIGHT_VO_SUBSYS_R_ADDRBASE + 0x50);
/* enable dpu_pixelclk0/1, dpu_hclk, dpu_aclk, dpu_cclk */
tmp = readl((void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
tmp |= 0x3e0;
writel(tmp, (void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
/* enable npu_axi_aclk, npu_core_clk */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
tmp |= 0x30;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
/* The boards other than the LightA board perform the bus down-speed operation */
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
tmp |= 0x2000;
writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
/* visys_aclk_m decrease frequency 792MHZ->594MHZ */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
tmp &= ~0x00100000;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
tmp &= ~0x000f0000;
tmp |= 0x00140000;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
/* vosys_aclk_m：792MHz->594MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
tmp &= ~0x00000020;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
tmp &= ~0x0000000f;
tmp |= 0x00000024;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
/* vpsys_axi_aclk：792MHz->594MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
tmp &= ~0x00001000;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
tmp &= ~0x00000f00;
tmp |= 0x00001400;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
/* npu_cclk：1000MHz->792MHz */
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
tmp |= 0x00000040;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
/* Enable dpu auto clock gating */
writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0);
writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1);
#endif
#endif
}
void ddr_clk_config(int ddr_freq)
{
/* Do nothing for FPGA */
}
|
