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This reverts commit adec30ace4cebb0554bb246b52eebaf37c1545c4.
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Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
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Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
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The data cache invalidation function for c9xx CPUs uses `dcache.cipa`
instruction. According to T-Head extension specification[1] section
3.1.5, this instruction also performs a cache clean along with the
invalidation.
On top of being incorrect, this leads to a serious issue on the
designware ethernet driver, where stalled cache may get flushed each
time we handle a new received packet[2]. As a result, received packet
are randomly corrupted with old cached data. This can easily be
reproduced by sending an ARP request to the device during a TFTP
transfer. The last TFTP block is treated as the ARP reply we just sent,
which makes U-Boot hang on the block.
Always use `dcache.ipa` instruction to invalidate dcache. Replace
existing usages of `dcache.ipa` with our implementation.
Note that this fix is slightly intrusive as it changes the cache
invalidation behavior in all drivers. However, I have not noticed any
side-effect during my tests.
[1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
[2] https://github.com/revyos/thead-u-boot/blob/918a8c89e056e3462031d6a498bb4fcc0c3526ce/drivers/net/designware.c#L475
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Signed-off-by: thead_admin <occ_thead@service.alibaba.com>
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Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
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Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
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