aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/kernel.zig22
-rw-r--r--src/lib/interrupts.zig6
-rw-r--r--src/lib/paging.zig10
-rw-r--r--src/lib/process.zig14
-rw-r--r--src/lib/riscv.zig (renamed from src/lib/instructions.zig)0
-rw-r--r--src/lib/sbi.zig16
-rw-r--r--src/lib/sbi/debug_console.zig4
-rw-r--r--src/lib/sbi/legacy.zig4
-rw-r--r--src/lib/sbi/sys_reset.zig2
-rw-r--r--src/lib/sbi/time.zig6
-rw-r--r--src/lib/syscall.zig4
11 files changed, 44 insertions, 44 deletions
diff --git a/src/kernel.zig b/src/kernel.zig
index c7c02cf..46bfcfa 100644
--- a/src/kernel.zig
+++ b/src/kernel.zig
@@ -5,12 +5,12 @@
const std = @import("std");
const Console = @import("lib/Console.zig");
const hwinfo = @import("lib/hwinfo.zig");
-const instructions = @import("lib/instructions.zig");
const interrupts = @import("lib/interrupts.zig");
const mem = @import("lib/mem.zig");
const paging = @import("lib/paging.zig");
const plic = @import("lib/plic.zig");
const process = @import("lib/process.zig");
+const riscv = @import("lib/riscv.zig");
const userinit = @import("lib/userinit.zig");
const Error = error{
@@ -22,11 +22,11 @@ const BootArgs = packed struct(usize) {
reserved: u48,
pub inline fn loadScratch() BootArgs {
- return @bitCast(instructions.sscratch.read());
+ return @bitCast(riscv.sscratch.read());
}
pub inline fn storeScratch(self: BootArgs) void {
- instructions.sscratch.write(@bitCast(self));
+ riscv.sscratch.write(@bitCast(self));
}
};
@@ -40,16 +40,16 @@ pub fn panic(msg: []const u8, error_return_trace: ?*std.builtin.StackTrace, ret_
@setCold(true);
- var sstatus = instructions.sstatus.read();
+ var sstatus = riscv.sstatus.read();
sstatus.user_interrupt_enable = 0;
sstatus.supervisor_interrupt_enable = 0;
- instructions.sstatus.write(sstatus);
+ riscv.sstatus.write(sstatus);
- instructions.sie.write(interrupts.Enable.none);
- instructions.sip.write(interrupts.Enable.none);
+ riscv.sie.write(interrupts.Enable.none);
+ riscv.sip.write(interrupts.Enable.none);
- const sepc = instructions.sepc.read();
- const stval = instructions.stval.read();
+ const sepc = riscv.sepc.read();
+ const stval = riscv.stval.read();
const console = Console.autoChoose() orelse halt();
const w = console.writer();
@@ -95,7 +95,7 @@ fn run(hart_id: usize) !noreturn {
try paging.init();
- instructions.satp.write(paging.kmem.satp(0));
+ riscv.satp.write(paging.kmem.satp(0));
asm volatile (
\\ la sp, _stack_end
@@ -134,7 +134,7 @@ fn pagedRun() !noreturn {
try w.print("Paging : Sv39\r\n", .{});
interrupts.init(hart_data.hart_id);
- instructions.sie.write(interrupts.Enable.all);
+ riscv.sie.write(interrupts.Enable.all);
try w.print("Interrupts : All\r\n", .{});
// var chunk_allocator = try mem.ChunkAllocator(.{ .auto_merge_free = true }).init(128);
diff --git a/src/lib/interrupts.zig b/src/lib/interrupts.zig
index 086e38e..e8fd219 100644
--- a/src/lib/interrupts.zig
+++ b/src/lib/interrupts.zig
@@ -5,10 +5,10 @@
const std = @import("std");
const Console = @import("Console.zig");
const TrapFrame = @import("TrapFrame.zig");
-const instructions = @import("instructions.zig");
const paging = @import("paging.zig");
const plic = @import("plic.zig");
const process = @import("process.zig");
+const riscv = @import("riscv.zig");
const syscall = @import("syscall.zig");
const time = @import("sbi/time.zig");
@@ -91,7 +91,7 @@ export fn handleTrap(epc: usize, cause_bits: usize, frame: *TrapFrame) usize {
const console = Console.autoChoose().?;
const w = console.writer();
- const status = instructions.sstatus.read();
+ const status = riscv.sstatus.read();
const cause: Cause = @bitCast(cause_bits);
@@ -287,7 +287,7 @@ pub fn init(hart_id: usize) void {
.general_purpose_registers = [_]usize{0} ** 32,
.floating_point_registers = [_]usize{0} ** 32,
.satp = 0,
- .stack_pointer = @ptrFromInt(instructions.stackPointer()),
+ .stack_pointer = @ptrFromInt(riscv.stackPointer()),
.hart_id = hart_id,
};
diff --git a/src/lib/paging.zig b/src/lib/paging.zig
index 84bc7dc..b6dbfe3 100644
--- a/src/lib/paging.zig
+++ b/src/lib/paging.zig
@@ -7,7 +7,7 @@
const std = @import("std");
const hwinfo = @import("hwinfo.zig");
-const instructions = @import("instructions.zig");
+const riscv = @import("riscv.zig");
// Defined by linker script.
pub const text_start = @extern(*anyopaque, .{ .name = "_text_start" });
@@ -582,7 +582,7 @@ pub fn free(memory: anytype) void {
pub fn zeroedAlloc(n: usize) AllocError![]align(page_size) u8 {
const ret = try alloc(n);
- const satp = instructions.satp.read();
+ const satp = riscv.satp.read();
if (satp.mode != .bare) {
const page_table: *Table = @ptrFromInt(satp.ppn << 12);
const start = @intFromPtr(ret.ptr);
@@ -590,7 +590,7 @@ pub fn zeroedAlloc(n: usize) AllocError![]align(page_size) u8 {
try page_table.identityMapRange(start, end, EntryFlags.readWrite);
}
- // Write zeroes in batches of 64-bit to reduce the amount of store instructions.
+ // Write zeroes in batches of 64-bit to reduce the amount of store riscv.
// The remainder / remaining bytes don't need to be accounted for
// because page_size (4096) is divisible by 8.
@@ -605,7 +605,7 @@ pub fn zeroedAlloc(n: usize) AllocError![]align(page_size) u8 {
}
pub fn setUserMemoryAccess(enable: bool) void {
- var sstatus = instructions.sstatus.read();
+ var sstatus = riscv.sstatus.read();
sstatus.supervisor_user_memory_access = @bitCast(enable);
- instructions.sstatus.write(sstatus);
+ riscv.sstatus.write(sstatus);
}
diff --git a/src/lib/process.zig b/src/lib/process.zig
index 8055936..dff5634 100644
--- a/src/lib/process.zig
+++ b/src/lib/process.zig
@@ -5,9 +5,9 @@
const builtin = @import("builtin");
const std = @import("std");
const TrapFrame = @import("TrapFrame.zig");
-const instructions = @import("instructions.zig");
const paging = @import("paging.zig");
const rethooks = @import("rethooks.zig");
+const riscv = @import("riscv.zig");
const time = @import("sbi/time.zig");
const Allocator = std.mem.Allocator;
const elf = std.elf;
@@ -104,7 +104,7 @@ pub const Info = struct {
pub fn terminate(
self: *Info,
) void {
- instructions.satp.write(paging.kmem.satp(0));
+ riscv.satp.write(paging.kmem.satp(0));
// Probably not always needed. Let's not take the risk for now.
asm volatile ("sfence.vma");
@@ -166,17 +166,17 @@ pub fn schedule() !noreturn {
pub fn switchTo(proc: *Info) noreturn {
proc.state = .active;
- var sstatus = instructions.sstatus.read();
+ var sstatus = riscv.sstatus.read();
sstatus.previous_privilege = .user;
sstatus.user_interrupt_enable = 0;
sstatus.supervisor_interrupt_enable = 0;
sstatus.user_prior_interrupt_enable = 1;
sstatus.supervisor_prior_interrupt_enable = 1;
- instructions.sstatus.write(sstatus);
+ riscv.sstatus.write(sstatus);
- instructions.sscratch.write(@intFromPtr(&proc.trap_frame));
- instructions.sepc.write(proc.pc);
- instructions.satp.write(proc.satp());
+ riscv.sscratch.write(@intFromPtr(&proc.trap_frame));
+ riscv.sepc.write(proc.pc);
+ riscv.satp.write(proc.satp());
// Probably not always needed. Let's not take the risk for now.
asm volatile (
diff --git a/src/lib/instructions.zig b/src/lib/riscv.zig
index 8c5a4ee..8c5a4ee 100644
--- a/src/lib/instructions.zig
+++ b/src/lib/riscv.zig
diff --git a/src/lib/sbi.zig b/src/lib/sbi.zig
index ddcb518..2b0506c 100644
--- a/src/lib/sbi.zig
+++ b/src/lib/sbi.zig
@@ -2,7 +2,7 @@
//
// SPDX-License-Identifier: AGPL-3.0-or-later
-const instructions = @import("instructions.zig");
+const riscv = @import("riscv.zig");
pub const Error = error{
Success,
@@ -64,7 +64,7 @@ pub const ImpId = enum(isize) {
};
pub fn specVer() !isize {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetSpecVer), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetSpecVer), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -73,7 +73,7 @@ pub fn specVer() !isize {
}
pub fn impId() !ImpId {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetImpId), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetImpId), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -82,7 +82,7 @@ pub fn impId() !ImpId {
}
pub fn impVer() !isize {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetImpVer), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetImpVer), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -91,7 +91,7 @@ pub fn impVer() !isize {
}
pub fn probeExt(ext_id: usize) !bool {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.ProbeExt), ext_id, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.ProbeExt), ext_id, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -100,7 +100,7 @@ pub fn probeExt(ext_id: usize) !bool {
}
pub fn mVendorId() !isize {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMVendorId), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMVendorId), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -109,7 +109,7 @@ pub fn mVendorId() !isize {
}
pub fn mArchId() !isize {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMarchId), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMarchId), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
@@ -118,7 +118,7 @@ pub fn mArchId() !isize {
}
pub fn mImpId() !isize {
- const ret = instructions.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMImpId), 0, 0, 0);
+ const ret = riscv.ecall(BaseExtId, @intFromEnum(BaseFnId.GetMImpId), 0, 0, 0);
if (ret.err != 0) {
return errorFromCode(ret.err);
}
diff --git a/src/lib/sbi/debug_console.zig b/src/lib/sbi/debug_console.zig
index 7959083..6c638e7 100644
--- a/src/lib/sbi/debug_console.zig
+++ b/src/lib/sbi/debug_console.zig
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: AGPL-3.0-or-later
const std = @import("std");
-const instructions = @import("../instructions.zig");
+const riscv = @import("../riscv.zig");
const sbi = @import("../sbi.zig");
const ExtId: usize = 0x4442434E;
@@ -17,7 +17,7 @@ const FnId = enum(usize) {
pub const Writer = std.io.Writer(void, sbi.Error, write);
fn write(_: void, bytes: []const u8) !usize {
- const ret = instructions.ecall(ExtId, @intFromEnum(FnId.Write), bytes.len, @intFromPtr(bytes.ptr), 0);
+ const ret = riscv.ecall(ExtId, @intFromEnum(FnId.Write), bytes.len, @intFromPtr(bytes.ptr), 0);
if (ret.err != 0) {
return sbi.errorFromCode(ret.err);
}
diff --git a/src/lib/sbi/legacy.zig b/src/lib/sbi/legacy.zig
index 4b392cf..517ccef 100644
--- a/src/lib/sbi/legacy.zig
+++ b/src/lib/sbi/legacy.zig
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: AGPL-3.0-or-later
const std = @import("std");
-const instructions = @import("../instructions.zig");
+const riscv = @import("../riscv.zig");
const sbi = @import("../sbi.zig");
const ExtId = enum(usize) {
@@ -22,7 +22,7 @@ pub const Writer = std.io.Writer(void, sbi.Error, write);
fn write(_: void, bytes: []const u8) !usize {
for (bytes) |byte| {
- const ret = instructions.ecall(@intFromEnum(ExtId.ConsolePutchar), 0, byte, 0, 0);
+ const ret = riscv.ecall(@intFromEnum(ExtId.ConsolePutchar), 0, byte, 0, 0);
if (ret.err != 0) {
return sbi.errorFromCode(ret.err);
}
diff --git a/src/lib/sbi/sys_reset.zig b/src/lib/sbi/sys_reset.zig
index 5651fba..a1571fd 100644
--- a/src/lib/sbi/sys_reset.zig
+++ b/src/lib/sbi/sys_reset.zig
@@ -2,7 +2,7 @@
//
// SPDX-License-Identifier: AGPL-3.0-or-later
-const instructions = @import("../instructions.zig");
+const riscv = @import("../riscv.zig");
const sbi = @import("../sbi.zig");
const ExtId: usize = 0x53525354;
diff --git a/src/lib/sbi/time.zig b/src/lib/sbi/time.zig
index f799d09..2f1f6a2 100644
--- a/src/lib/sbi/time.zig
+++ b/src/lib/sbi/time.zig
@@ -4,7 +4,7 @@
const std = @import("std");
const hwinfo = @import("../hwinfo.zig");
-const instructions = @import("../instructions.zig");
+const riscv = @import("../riscv.zig");
const sbi = @import("../sbi.zig");
const ExtId: usize = 0x54494d45;
@@ -20,12 +20,12 @@ pub const Error = error{
pub fn setTimer(stime_absolute: u64) !void {
if (!try sbi.probeExt(ExtId)) return sbi.Error.NotSupported;
- const ret = instructions.ecall(ExtId, @intFromEnum(FnId.SetTimer), stime_absolute, 0, 0);
+ const ret = riscv.ecall(ExtId, @intFromEnum(FnId.SetTimer), stime_absolute, 0, 0);
if (ret.err != 0) return sbi.errorFromCode(ret.err);
}
pub fn interruptInMillis(millis: u64) !void {
- const time = instructions.time.read();
+ const time = riscv.time.read();
var cpus = try hwinfo.byKind(.cpus);
const frequency = try cpus.next() orelse return error.NoCpusHwInfo;
diff --git a/src/lib/syscall.zig b/src/lib/syscall.zig
index 57ba258..0d0ca03 100644
--- a/src/lib/syscall.zig
+++ b/src/lib/syscall.zig
@@ -5,10 +5,10 @@
const std = @import("std");
const Console = @import("Console.zig");
const TrapFrame = @import("TrapFrame.zig");
-const instructions = @import("instructions.zig");
const mem = @import("mem.zig");
const paging = @import("paging.zig");
const process = @import("process.zig");
+const riscv = @import("riscv.zig");
pub const Error = error{
Unimplemented,
@@ -64,7 +64,7 @@ fn consoleWrite(trap_frame: *const TrapFrame) !usize {
const vaddr = trap_frame.general_purpose_registers[10];
const len = trap_frame.general_purpose_registers[11];
- const procmem: *paging.Table = @ptrFromInt(instructions.satp.read().ppn << 12);
+ const procmem: *paging.Table = @ptrFromInt(riscv.satp.read().ppn << 12);
const flags = paging.EntryFlags.userReadOnly;
const paddr = procmem.translate(vaddr, flags) orelse {
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-10 10:23:59 +0000