1 files changed, 51 insertions, 8 deletions

diff --git a/src/interrupts.zig b/src/interrupts.zig
index bdc1c5f..4f83fda 100644
--- a/src/interrupts.zig
+++ b/src/interrupts.zig
@@ -4,6 +4,8 @@
 
 const std = @import("std");
 
+const instructions = @import("instructions.zig");
+
 pub const SupervisorTrapVector = packed struct(usize) {
     pub const Mode = enum(u2) {
         direct = 0,
@@ -21,6 +23,30 @@ pub const SupervisorTrapVector = packed struct(usize) {
     }
 };
 
+pub const Enable = packed struct(usize) {
+    u_software: u1,
+    s_software: u1,
+    reserved0: u2,
+    u_timer: u1,
+    s_timer: u1,
+    reserved1: u2,
+    u_external: u1,
+    s_external: u1,
+    reserved2: u54,
+
+    pub const all = .{
+        .u_software = 1,
+        .s_software = 1,
+        .reserved0 = 0,
+        .u_timer = 1,
+        .s_timer = 1,
+        .reserved1 = 0,
+        .u_external = 1,
+        .s_external = 1,
+        .reserved2 = 0,
+    };
+};
+
 pub const TrapFrame = extern struct {
     general_purpose_registers: [32]usize, // Offset: 0
     floating_point_registers: [32]usize, // Offset: 256
@@ -29,15 +55,23 @@ pub const TrapFrame = extern struct {
     hart_id: usize, // Offset: 528
 };
 
-export fn s_trap(epc: usize, tval: usize, cause: usize, hart_id: usize, status: usize, frame: *TrapFrame) usize {}
+export fn supervisor_trap(epc: usize, tval: usize, cause: usize, hart_id: usize, status: usize, frame: *TrapFrame) usize {
+    _ = &epc;
+    _ = &tval;
+    _ = &cause;
+    _ = &hart_id;
+    _ = &status;
+    _ = &frame;
+    return 0;
+}
 
-export fn supervisor_trap_vector() linksection(".stvec") callconv(.Naked) noreturn {
+export fn supervisor_trap_vector() align(4) callconv(.Naked) noreturn {
     asm volatile (
         \\ csrrw t6, sscratch, t6
     );
 
     inline for (1..31) |i| {
-        save_general_purpose(i);
+        save_general_purpose(i, null);
     }
 
     asm volatile (
@@ -53,18 +87,18 @@ export fn supervisor_trap_vector() linksection(".stvec") callconv(.Naked) noretu
         \\ csrr a0, sepc
         \\ csrr a1, stval
         \\ csrr a2, scause
-        \\ csrr a3, shartid
+        \\ csrr a3, mhartid
         \\ csrr a4, sstatus
         \\ mv a5, t5
         \\ ld sp, 520(t5)
-        \\ call s_trap
+        \\ call supervisor_trap
         \\
         \\ csrw sepc, a0
         \\ csrr t6, sscratch
     );
 
     inline for (1..32) |i| {
-        load_general_purpose(i);
+        load_general_purpose(i, null);
     }
 
     asm volatile (
@@ -75,13 +109,22 @@ export fn supervisor_trap_vector() linksection(".stvec") callconv(.Naked) noretu
 inline fn save_general_purpose(comptime i: u5, comptime base_register: ?u5) void {
     comptime var buf = [_]u8{0} ** 17;
 
-    const offset = i * @sizeOf(usize);
+    const offset = @as(usize, i) * @sizeOf(usize);
     asm volatile (std.fmt.bufPrint(buf[0..], "sd x{d}, {d}(x{d})", .{ i, offset, base_register orelse 31 }) catch unreachable);
 }
 
 inline fn load_general_purpose(comptime i: u5, comptime base_register: ?u5) void {
     comptime var buf = [_]u8{0} ** 17;
 
-    const offset = i * @sizeOf(usize);
+    const offset = @as(usize, i) * @sizeOf(usize);
     asm volatile (std.fmt.bufPrint(buf[0..], "ld x{d}, {d}(x{d})", .{ i, offset, base_register orelse 31 }) catch unreachable);
 }
+
+pub fn init() void {
+    asm volatile (
+        \\ la t0, supervisor_trap_vector
+        \\ csrw stvec, t0
+    );
+}
+
+pub const setEnabled = instructions.setCsrFn(Enable, "sie").?;