1 files changed, 176 insertions, 0 deletions
diff --git a/src/pci.zig b/src/pci.zig
index da8b33c..8299f8a 100644
--- a/src/pci.zig
+++ b/src/pci.zig
@@ -463,6 +463,182 @@ pub const PCI2CardBusHeader = packed struct(u448) {
     subsystem_device_id: u16,
     subsystem_vendor_id: u16,
     pc_card_legacy_mode_16_bit_base_addr: u32,
+
+    pub fn getCardbusSocketExCaBaseAddr(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.cardbus_socket_exca_base_addr);
+    }
+
+    pub fn getCapabilitiesListOffset(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.capabilities_list_offset);
+    }
+
+    pub fn getReserved0(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.reserved0);
+    }
+
+    pub fn getSecondaryStatus(self: *const volatile PCI2CardBusHeader) u16 {
+        return mem.littleToNative(u16, self.secondary_status);
+    }
+
+    pub fn getPCIBusNumber(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.pci_bus_number);
+    }
+
+    pub fn getCardBusBusNumber(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.cardbus_bus_number);
+    }
+
+    pub fn getSubordinateBusNumber(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.subordinate_bus_number);
+    }
+
+    pub fn getCardBusLatencyTimer(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.cardbus_latency_timer);
+    }
+
+    pub fn getMemoryBaseAddr0(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.memory_base_addr0);
+    }
+
+    pub fn getMemoryLimit0(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.memory_limit0);
+    }
+
+    pub fn getMemoryBaseAddr1(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.memory_base_addr1);
+    }
+
+    pub fn getMemoryLimit1(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.memory_limit1);
+    }
+
+    pub fn getIOBaseAddr0(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.io_base_addr0);
+    }
+
+    pub fn getIOLimit0(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.io_limit0);
+    }
+
+    pub fn getIOBaseAddr1(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.io_base_addr1);
+    }
+
+    pub fn getIOLimit1(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.io_limit1);
+    }
+
+    pub fn getInterruptLine(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.interrupt_line);
+    }
+
+    pub fn getInterruptPIN(self: *const volatile PCI2CardBusHeader) u8 {
+        return mem.littleToNative(u8, self.interrupt_pin);
+    }
+
+    pub fn getBridgeControl(self: *const volatile PCI2CardBusHeader) u16 {
+        return mem.littleToNative(u16, self.bridge_control);
+    }
+
+    pub fn getSubsystemDeviceID(self: *const volatile PCI2CardBusHeader) u16 {
+        return mem.littleToNative(u16, self.subsystem_device_id);
+    }
+
+    pub fn getSubsystemVendorID(self: *const volatile PCI2CardBusHeader) u16 {
+        return mem.littleToNative(u16, self.subsystem_vendor_id);
+    }
+
+    pub fn getPCCardLegacyMode16BitBaseAddr(self: *const volatile PCI2CardBusHeader) u32 {
+        return mem.littleToNative(u32, self.pc_card_legacy_mode_16_bit_base_addr);
+    }
+
+    pub fn setCardbusSocketExCaBaseAddr(self: *volatile PCI2CardBusHeader, new_cardbus_socket_exca_base_addr: u32) void {
+        self.cardbus_socket_exca_base_addr = mem.nativeToLittle(u32, new_cardbus_socket_exca_base_addr);
+    }
+
+    pub fn setCapabilitiesListOffset(self: *volatile PCI2CardBusHeader, new_capabilities_list_offset: u8) void {
+        self.capabilities_list_offset = mem.nativeToLittle(u8, new_capabilities_list_offset);
+    }
+
+    pub fn setReserved0(self: *volatile PCI2CardBusHeader, new_reserved0: u8) void {
+        self.reserved0 = mem.nativeToLittle(u8, new_reserved0);
+    }
+
+    pub fn setSecondaryStatus(self: *volatile PCI2CardBusHeader, new_secondary_status: u16) void {
+        self.secondary_status = mem.nativeToLittle(u16, new_secondary_status);
+    }
+
+    pub fn setPCIBusNumber(self: *volatile PCI2CardBusHeader, new_pci_bus_number: u8) void {
+        self.pci_bus_number = mem.nativeToLittle(u8, new_pci_bus_number);
+    }
+
+    pub fn setCardBusBusNumber(self: *volatile PCI2CardBusHeader, new_cardbus_bus_number: u8) void {
+        self.cardbus_bus_number = mem.nativeToLittle(u8, new_cardbus_bus_number);
+    }
+
+    pub fn setSubordinateBusNumber(self: *volatile PCI2CardBusHeader, new_subordinate_bus_number: u8) void {
+        self.subordinate_bus_number = mem.nativeToLittle(u8, new_subordinate_bus_number);
+    }
+
+    pub fn setCardBusLatencyTimer(self: *volatile PCI2CardBusHeader, new_cardbus_latency_timer: u8) void {
+        self.cardbus_latency_timer = mem.nativeToLittle(u8, new_cardbus_latency_timer);
+    }
+
+    pub fn setMemoryBaseAddr0(self: *volatile PCI2CardBusHeader, new_memory_base_addr0: u32) void {
+        self.memory_base_addr0 = mem.nativeToLittle(u32, new_memory_base_addr0);
+    }
+
+    pub fn setMemoryLimit0(self: *volatile PCI2CardBusHeader, new_memory_limit0: u32) void {
+        self.memory_limit0 = mem.nativeToLittle(u32, new_memory_limit0);
+    }
+
+    pub fn setMemoryBaseAddr1(self: *volatile PCI2CardBusHeader, new_memory_base_addr1: u32) void {
+        self.memory_base_addr1 = mem.nativeToLittle(u32, new_memory_base_addr1);
+    }
+
+    pub fn setMemoryLimit1(self: *volatile PCI2CardBusHeader, new_memory_limit1: u32) void {
+        self.memory_limit1 = mem.nativeToLittle(u32, new_memory_limit1);
+    }
+
+    pub fn setIOBaseAddr0(self: *volatile PCI2CardBusHeader, new_io_base_addr0: u32) void {
+        self.io_base_addr0 = mem.nativeToLittle(u32, new_io_base_addr0);
+    }
+
+    pub fn setIOLimit0(self: *volatile PCI2CardBusHeader, new_io_limit0: u32) void {
+        self.io_limit0 = mem.nativeToLittle(u32, new_io_limit0);
+    }
+
+    pub fn setIOBaseAddr1(self: *volatile PCI2CardBusHeader, new_io_base_addr1: u32) void {
+        self.io_base_addr1 = mem.nativeToLittle(u32, new_io_base_addr1);
+    }
+
+    pub fn setIOLimit1(self: *volatile PCI2CardBusHeader, new_io_limit1: u32) void {
+        self.io_limit1 = mem.nativeToLittle(u32, new_io_limit1);
+    }
+
+    pub fn setInterruptLine(self: *volatile PCI2CardBusHeader, new_interrupt_line: u8) void {
+        self.interrupt_line = mem.nativeToLittle(u8, new_interrupt_line);
+    }
+
+    pub fn setInterruptPIN(self: *volatile PCI2CardBusHeader, new_interrupt_pin: u8) void {
+        self.interrupt_pin = mem.nativeToLittle(u8, new_interrupt_pin);
+    }
+
+    pub fn setBridgeControl(self: *volatile PCI2CardBusHeader, new_bridge_control: u16) void {
+        self.bridge_control = mem.nativeToLittle(u16, new_bridge_control);
+    }
+
+    pub fn setSubsystemDeviceID(self: *volatile PCI2CardBusHeader, new_subsystem_device_id: u16) void {
+        self.subsystem_device_id = mem.nativeToLittle(u16, new_subsystem_device_id);
+    }
+
+    pub fn setSubsystemVendorID(self: *volatile PCI2CardBusHeader, new_subsystem_vendor_id: u16) void {
+        self.subsystem_vendor_id = mem.nativeToLittle(u16, new_subsystem_vendor_id);
+    }
+
+    pub fn setPCCardLegacyMode16BitBaseAddr(self: *volatile PCI2CardBusHeader, new_pc_card_legacy_mode_16_bit_base_addr: u32) void {
+        self.pc_card_legacy_mode_16_bit_base_addr = mem.nativeToLittle(u32, new_pc_card_legacy_mode_16_bit_base_addr);
+    }
 };
 
 pub const CfgSpace = packed struct(u576) {