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-rw-r--r--src/interrupts.zig16
1 files changed, 14 insertions, 2 deletions
diff --git a/src/interrupts.zig b/src/interrupts.zig
index 4cd6947..6823d8b 100644
--- a/src/interrupts.zig
+++ b/src/interrupts.zig
@@ -106,7 +106,7 @@ export fn supervisor_trap(epc: usize, tval: usize, cause_bits: usize, hart_id: u
.supervisor_timer => w.print("Hart {d}: Supervisor timer interrupt\r\n", .{hart_id}) catch while (true) {},
.supervisor_external => w.print("Hart {d}: Supervisor external interrupt\r\n", .{hart_id}) catch while (true) {},
else => {
- w.print("Hart {d}: Unhandled asynchronous interrupt\r\n", .{hart_id}) catch while (true) {};
+ w.print("Hart {d}: Unhandled asynchronous interrupt: {d}\r\n", .{ hart_id, cause.num }) catch while (true) {};
while (true) {}
},
}
@@ -116,6 +116,18 @@ export fn supervisor_trap(epc: usize, tval: usize, cause_bits: usize, hart_id: u
w.print("Hart {d}: Illegal instruction\r\n", .{hart_id}) catch while (true) {};
while (true) {}
},
+ .instruction_access_fault => {
+ w.print("Hart {d}: Instruction access fault, tval = 0x{x:0>16}\r\n", .{ hart_id, tval }) catch while (true) {};
+ return epc + 4;
+ },
+ .load_access_fault => {
+ w.print("Hart {d}: Load access fault, tval = 0x{x:0>16}\r\n", .{ hart_id, tval }) catch while (true) {};
+ return epc + 4;
+ },
+ .store_or_amo_access_fault => {
+ w.print("Hart {d}: Store/AMO access fault, tval = 0x{x:0>16}\r\n", .{ hart_id, tval }) catch while (true) {};
+ return epc + 4;
+ },
.ecall => {
w.print("Hart {d}: Environment call from U-mode\r\n", .{hart_id}) catch while (true) {};
return epc + 4;
@@ -133,7 +145,7 @@ export fn supervisor_trap(epc: usize, tval: usize, cause_bits: usize, hart_id: u
return epc + 4;
},
else => {
- w.print("Hart {d}: Unhandled synchronous interrupt\r\n", .{hart_id}) catch while (true) {};
+ w.print("Hart {d}: Unhandled synchronous interrupt: {d}\r\n", .{ hart_id, cause.num }) catch while (true) {};
while (true) {}
},
}