process: Add U-mode switcher

1 files changed, 68 insertions, 2 deletions

diff --git a/src/process.zig b/src/process.zig
index b5de131..61103bf 100644
--- a/src/process.zig
+++ b/src/process.zig
@@ -4,14 +4,16 @@
 
 const std = @import("std");
 
+const instructions = @import("instructions.zig");
 const interrupts = @import("interrupts.zig");
+const mem = @import("mem.zig");
 const paging = @import("paging.zig");
 
 const num_stack_pages = 2;
 
 var next_pid = 1;
 var previous_scheduled = 1;
-var list = std.mem.zeroInit(std.DoublyLinkedList(Info));
+var list = std.mem.zeroInit(std.DoublyLinkedList(*Info));
 
 pub const State = enum {
     waiting,
@@ -21,7 +23,7 @@ pub const State = enum {
 };
 
 pub const Info = extern struct {
-    id: u32,
+    id: u16,
     trap_frame: interrupts.TrapFrame,
     stack: [*]u8,
     pc: usize,
@@ -33,6 +35,10 @@ pub const Info = extern struct {
         try self.page_table.unmap();
         try paging.free(self.page_table);
     }
+
+    pub fn satp(self: *const Info) paging.Satp {
+        return mem.satp(self.page_table, self.pid);
+    }
 };
 
 fn new(entry: *fn () void) !Info {
@@ -75,3 +81,63 @@ pub fn nextScheduled() ?Info {
 
     return null;
 }
+
+fn switchTo(proc: *const Info) noreturn {
+    instructions.setSscratch(@intFromPtr(&proc.trap_frame));
+
+    asm volatile (
+        \\ csrr t0, sstatus
+        \\ li t1, 0x100
+        \\ noti t1, t1
+        \\ andi t0, t0, t1
+        \\ csrw sstatus, t0
+        ::: "t0", "t1");
+
+    instructions.setSepc(proc.pc);
+    instructions.setSatp(proc.buildSatp());
+
+    // Probably not always needed. Let's not take the risk for now.
+    asm volatile (
+        \\ sfence.vma
+    );
+
+    asm volatile (
+        \\ csrr t6, sscratch
+        \\
+        \\ ld x1, 8(t6)
+        \\ ld x2, 16(t6)
+        \\ ld x3, 24(t6)
+        \\ ld x4, 32(t6)
+        \\ ld x5, 40(t6)
+        \\ ld x6, 48(t6)
+        \\ ld x7, 56(t6)
+        \\ ld x8, 64(t6)
+        \\ ld x9, 72(t6)
+        \\ ld x10, 80(t6)
+        \\ ld x11, 88(t6)
+        \\ ld x12, 96(t6)
+        \\ ld x13, 104(t6)
+        \\ ld x14, 112(t6)
+        \\ ld x15, 120(t6)
+        \\ ld x16, 128(t6)
+        \\ ld x17, 136(t6)
+        \\ ld x18, 144(t6)
+        \\ ld x19, 152(t6)
+        \\ ld x20, 160(t6)
+        \\ ld x21, 168(t6)
+        \\ ld x22, 176(t6)
+        \\ ld x23, 184(t6)
+        \\ ld x24, 192(t6)
+        \\ ld x25, 200(t6)
+        \\ ld x26, 208(t6)
+        \\ ld x27, 216(t6)
+        \\ ld x28, 224(t6)
+        \\ ld x29, 232(t6)
+        \\ ld x30, 240(t6)
+        \\ ld x31, 248(t6)
+        \\
+        \\ sret
+    );
+}
+
+pub fn demo() void {}