process: Use simple rotating scheduler

3 files changed, 22 insertions, 11 deletions

diff --git a/src/interrupts.zig b/src/interrupts.zig
index a2233aa..de03337 100644
--- a/src/interrupts.zig
+++ b/src/interrupts.zig
@@ -7,6 +7,7 @@ const std = @import("std");
 const debug_console = @import("sbi/debug_console.zig");
 const instructions = @import("instructions.zig");
 const plic = @import("plic.zig");
+const process = @import("process.zig");
 const syscall = @import("syscall.zig");
 const time = @import("sbi/time.zig");
 const trap = @import("trap.zig");
@@ -101,6 +102,7 @@ export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize,
             .supervisor_software => w.print("Hart {d}: Software interrupt\r\n", .{hart_id}) catch while (true) {},
             .supervisor_timer => {
                 time.interruptInSeconds(null, 1) catch while (true) {};
+                schedule() catch while (true) {};
             },
             .supervisor_external => {
                 const context: u14 = @intCast(2 * hart_id + 1);
@@ -266,6 +268,14 @@ export fn supervisorTrapVector() align(4) callconv(.Naked) noreturn {
     );
 }
 
+fn schedule() noreturn {
+    if (process.next()) |next| {
+        process.switchTo(next);
+    }
+
+    while (true) asm volatile ("wfi");
+}
+
 pub fn init() void {
     trap_frame = .{
         .general_purpose_registers = [_]usize{0} ** 32,
diff --git a/src/main.zig b/src/main.zig
index 058fe36..ec33a4c 100644
--- a/src/main.zig
+++ b/src/main.zig
@@ -128,7 +128,7 @@ fn run(hart_id: usize, fdt_blob: *fdt.RawHeader, w: debug_console.Writer) !noret
     try w.print("Segfault successful\r\n", .{});
 
     try w.print("Enter process demo\r\n", .{});
-    try process.demo();
+    try process.demo(allocator);
 
     while (true) {
         asm volatile ("wfi");
diff --git a/src/process.zig b/src/process.zig
index 9577bc3..a6217c6 100644
--- a/src/process.zig
+++ b/src/process.zig
@@ -5,14 +5,13 @@
 const std = @import("std");
 
 const instructions = @import("instructions.zig");
-const interrupts = @import("interrupts.zig");
 const paging = @import("paging.zig");
 const trap = @import("trap.zig");
 
 const num_stack_pages = 2;
 
 var next_pid: u16 = 1;
-var list = std.mem.zeroInit(std.DoublyLinkedList(*Info));
+var list = std.mem.zeroInit(std.DoublyLinkedList(Info), .{});
 
 pub const State = enum(u8) {
     waiting,
@@ -73,16 +72,16 @@ fn new(entry: usize) !Info {
     return proc;
 }
 
-pub fn nextScheduled() ?Info {
-    if (list.popFirst()) |next| {
-        list.append(next);
-        return next.data;
+pub fn next() ?*Info {
+    if (list.popFirst()) |info| {
+        list.append(info);
+        return &info.data;
     }
 
     return null;
 }
 
-fn switchTo(proc: *const Info) noreturn {
+pub fn switchTo(proc: *const Info) noreturn {
     instructions.setSscratch(@intFromPtr(&proc.trap_frame));
 
     asm volatile (
@@ -142,7 +141,7 @@ fn switchTo(proc: *const Info) noreturn {
     unreachable;
 }
 
-pub fn demo() !void {
+pub fn demo(allocator: std.mem.Allocator) !void {
     const entry: [*]u8 = @alignCast(@ptrCast(try paging.zeroedAlloc(1)));
     defer paging.free(@ptrCast(entry)) catch {};
 
@@ -151,8 +150,10 @@ pub fn demo() !void {
     entry[2] = 0x00;
     entry[3] = 0x00;
 
-    var proc = try new(@intFromPtr(entry));
-    switchTo(&proc);
+    const proc = try new(@intFromPtr(entry));
+    const proc_node = try allocator.create(std.DoublyLinkedList(Info).Node);
+    proc_node.data = proc;
+    list.prepend(proc_node);
 
     while (true) asm volatile ("wfi");
 }