Update to zig 0.12.0

1 files changed, 4 insertions, 4 deletions

diff --git a/src/pci.zig b/src/pci.zig
index eae1a14..7ee8f7b 100644
--- a/src/pci.zig
+++ b/src/pci.zig
@@ -765,8 +765,8 @@ pub fn controllerFromFdt(dt: *const fdt.Tree) !Controller {
     const address_cells_bytes = soc[1].props.get("#address-cells") orelse return Error.NoAddrCells;
     const size_cells_bytes = soc[1].props.get("#size-cells") orelse return Error.NoSizeCells;
 
-    const address_cells = 16 * std.mem.readInt(u32, address_cells_bytes[0..4], .Big);
-    const size_cells = 16 * std.mem.readInt(u32, size_cells_bytes[0..4], .Big);
+    const address_cells = 16 * std.mem.readInt(u32, address_cells_bytes[0..4], .big);
+    const size_cells = 16 * std.mem.readInt(u32, size_cells_bytes[0..4], .big);
 
     var results = fdt.findNode(soc[1].subnodes.items, "pci");
     const node = results.next() orelse return Error.NoPcinode;
@@ -779,8 +779,8 @@ pub fn controllerFromFdt(dt: *const fdt.Tree) !Controller {
 
     if (n < 1) return Error.NoReg;
 
-    const ptr: [*]u8 = @ptrFromInt(unitAddr + std.mem.readVarInt(usize, reg[0..(address_cells / 8)], .Big));
-    const len = std.mem.readVarInt(usize, reg[(address_cells / 8) .. (size_cells / 8) + (address_cells / 8)], .Big);
+    const ptr: [*]u8 = @ptrFromInt(unitAddr + std.mem.readVarInt(usize, reg[0..(address_cells / 8)], .big));
+    const len = std.mem.readVarInt(usize, reg[(address_cells / 8) .. (size_cells / 8) + (address_cells / 8)], .big);
     const slice = ptr[0..len];
 
     const compatible = node.props.get("compatible") orelse return Error.NoCompatInfo;