Rename instructions.zig => riscv.zig

1 files changed, 7 insertions, 7 deletions

diff --git a/src/lib/process.zig b/src/lib/process.zig
index 8055936..dff5634 100644
--- a/src/lib/process.zig
+++ b/src/lib/process.zig
@@ -5,9 +5,9 @@
 const builtin = @import("builtin");
 const std = @import("std");
 const TrapFrame = @import("TrapFrame.zig");
-const instructions = @import("instructions.zig");
 const paging = @import("paging.zig");
 const rethooks = @import("rethooks.zig");
+const riscv = @import("riscv.zig");
 const time = @import("sbi/time.zig");
 const Allocator = std.mem.Allocator;
 const elf = std.elf;
@@ -104,7 +104,7 @@ pub const Info = struct {
     pub fn terminate(
         self: *Info,
     ) void {
-        instructions.satp.write(paging.kmem.satp(0));
+        riscv.satp.write(paging.kmem.satp(0));
         // Probably not always needed. Let's not take the risk for now.
         asm volatile ("sfence.vma");
 
@@ -166,17 +166,17 @@ pub fn schedule() !noreturn {
 pub fn switchTo(proc: *Info) noreturn {
     proc.state = .active;
 
-    var sstatus = instructions.sstatus.read();
+    var sstatus = riscv.sstatus.read();
     sstatus.previous_privilege = .user;
     sstatus.user_interrupt_enable = 0;
     sstatus.supervisor_interrupt_enable = 0;
     sstatus.user_prior_interrupt_enable = 1;
     sstatus.supervisor_prior_interrupt_enable = 1;
-    instructions.sstatus.write(sstatus);
+    riscv.sstatus.write(sstatus);
 
-    instructions.sscratch.write(@intFromPtr(&proc.trap_frame));
-    instructions.sepc.write(proc.pc);
-    instructions.satp.write(proc.satp());
+    riscv.sscratch.write(@intFromPtr(&proc.trap_frame));
+    riscv.sepc.write(proc.pc);
+    riscv.satp.write(proc.satp());
 
     // Probably not always needed. Let's not take the risk for now.
     asm volatile (