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authorHimbeer <himbeer@disroot.org>2024-06-04 12:39:05 +0200
committerHimbeer <himbeer@disroot.org>2024-06-04 12:39:29 +0200
commit45e3c701ea49ba7474af355fe0ddd9b0f7baa841 (patch)
tree2642677e958cb56bc2c2827878635f94e55a7669 /src/lib/interrupts.zig
parent88ab08bfff60c7ef15ae81e2ab0bd802607f95be (diff)
interrupts: Use kernel trap frame to get correct hart ID
Fixes #24.
Diffstat (limited to 'src/lib/interrupts.zig')
-rw-r--r--src/lib/interrupts.zig45
1 files changed, 21 insertions, 24 deletions
diff --git a/src/lib/interrupts.zig b/src/lib/interrupts.zig
index 8c6b930..1d98b06 100644
--- a/src/lib/interrupts.zig
+++ b/src/lib/interrupts.zig
@@ -108,7 +108,7 @@ pub const Sstatus = packed struct(usize) {
sd: u1,
};
-export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize, status: Sstatus, frame: *trap.Frame) usize {
+export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, status: Sstatus, frame: *trap.Frame) usize {
_ = &status;
_ = &frame;
@@ -119,7 +119,7 @@ export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize,
if (cause.isAsync()) {
switch (@as(AsyncCause, @enumFromInt(cause.num))) {
- .supervisor_software => w.print("Hart {d}: Software interrupt\r\n", .{hart_id}) catch unreachable,
+ .supervisor_software => w.print("Hart {d}: Software interrupt\r\n", .{frame.hart_id}) catch unreachable,
.supervisor_timer => {
if (status.previous_privilege == 0) {
// Trapped from U-mode, update pc for next time slice.
@@ -132,65 +132,65 @@ export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize,
process.list.last.?.data.state = .waiting;
schedule() catch |err| {
- std.debug.panic("Hart {d}: Unable to schedule next process: {any}", .{ hart_id, err });
+ std.debug.panic("Hart {d}: Unable to schedule next process: {any}", .{ frame.hart_id, err });
};
}
// Don't interrupt kernel code, it may never run otherwise.
},
.supervisor_external => {
- const context: u14 = @intCast(2 * hart_id + 1);
+ const context: u14 = @intCast(2 * frame.hart_id + 1);
const external_cause = plic.default.claim(context) catch |err| {
- std.debug.panic("Hart {d}: Unable to claim external interrupt: {any}", .{ hart_id, err });
+ std.debug.panic("Hart {d}: Unable to claim external interrupt: {any}", .{ frame.hart_id, err });
};
if (external_cause) |source| {
- w.print("Hart {d}: External interrupt: 0x{x}\r\n", .{ hart_id, source }) catch unreachable;
+ w.print("Hart {d}: External interrupt: 0x{x}\r\n", .{ frame.hart_id, source }) catch unreachable;
handleExternal(source);
plic.default.complete(context, source) catch |err| {
- std.debug.panic("Hart {d}: Unable to complete external interrupt: {any}", .{ hart_id, err });
+ std.debug.panic("Hart {d}: Unable to complete external interrupt: {any}", .{ frame.hart_id, err });
};
}
},
else => {
- std.debug.panic("Hart {d}: Unhandled asynchronous interrupt: {d}", .{ hart_id, cause.num });
+ std.debug.panic("Hart {d}: Unhandled asynchronous interrupt: {d}", .{ frame.hart_id, cause.num });
},
}
} else {
switch (@as(SyncCause, @enumFromInt(cause.num))) {
.illegal_instruction => {
- std.debug.panic("Hart {d}: Illegal instruction, EPC = 0x{x:0>16}", .{ hart_id, epc });
+ std.debug.panic("Hart {d}: Illegal instruction, EPC = 0x{x:0>16}", .{ frame.hart_id, epc });
},
.instruction_access_fault => {
- std.debug.panic("Hart {d}: Instruction access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Instruction access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
.load_access_fault => {
- std.debug.panic("Hart {d}: Load access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Load access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
.store_or_amo_access_fault => {
- std.debug.panic("Hart {d}: Store/AMO access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Store/AMO access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
.ecall => {
syscall.handle(frame) catch |err| switch (err) {
syscall.Error.UnknownSyscall => {
const a0 = frame.general_purpose_registers[10];
- w.print("Hart {d}: Unknown syscall, a0 = 0x{x:0>16}\r\n", .{ hart_id, a0 }) catch unreachable;
+ w.print("Hart {d}: Unknown syscall, a0 = 0x{x:0>16}\r\n", .{ frame.hart_id, a0 }) catch unreachable;
},
};
return epc + 4;
},
.instruction_page_fault => {
- std.debug.panic("Hart {d}: Instruction page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Instruction page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
.load_page_fault => {
- std.debug.panic("Hart {d}: Load page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Load page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
.store_or_amo_page_fault => {
- std.debug.panic("Hart {d}: Store/AMO page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval });
+ std.debug.panic("Hart {d}: Store/AMO page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ frame.hart_id, epc, tval });
},
else => {
- std.debug.panic("Hart {d}: Unhandled synchronous interrupt: {d}, EPC = 0x{x:0>16}", .{ hart_id, cause.num, epc });
+ std.debug.panic("Hart {d}: Unhandled synchronous interrupt: {d}, EPC = 0x{x:0>16}", .{ frame.hart_id, cause.num, epc });
},
}
}
@@ -247,11 +247,8 @@ export fn supervisorTrapVector() align(4) callconv(.Naked) noreturn {
\\ csrr a0, sepc
\\ csrr a1, stval
\\ csrr a2, scause
- // \\ csrr a3, mhartid
- // Use zero for the hart id until a solution is found.
- \\ mv a3, zero
- \\ csrr a4, sstatus
- \\ mv a5, t5
+ \\ csrr a3, sstatus
+ \\ mv a4, t5
\\ la sp, _stvec_stack_end
\\ call handleTrap
\\
@@ -304,13 +301,13 @@ fn schedule() !noreturn {
return process.Error.EmptySchedule;
}
-pub fn init() void {
+pub fn init(hart_id: usize) void {
trap_frame = .{
.general_purpose_registers = [_]usize{0} ** 32,
.floating_point_registers = [_]usize{0} ** 32,
.satp = 0,
.stack_pointer = @ptrFromInt(instructions.stackPointer()),
- .hart_id = 0,
+ .hart_id = hart_id,
};
asm volatile (