diff options
author | Himbeer <himbeer@disroot.org> | 2024-05-13 19:18:34 +0200 |
---|---|---|
committer | Himbeer <himbeer@disroot.org> | 2024-05-13 19:18:34 +0200 |
commit | 8a5184ea81ea7a7771919d5db6cce9d61fe957a2 (patch) | |
tree | 5feb55a620ec7600e581ba4595859012e5afd6f6 | |
parent | 373c0c7b3b3f1689bf75ed2c621aa1a07d77675b (diff) |
interrupts: Panic on all potentially dangerous cases
-rw-r--r-- | src/interrupts.zig | 46 |
1 files changed, 22 insertions, 24 deletions
diff --git a/src/interrupts.zig b/src/interrupts.zig index de03337..2a6bf34 100644 --- a/src/interrupts.zig +++ b/src/interrupts.zig @@ -6,6 +6,7 @@ const std = @import("std"); const debug_console = @import("sbi/debug_console.zig"); const instructions = @import("instructions.zig"); +const paging = @import("paging.zig"); const plic = @import("plic.zig"); const process = @import("process.zig"); const syscall = @import("syscall.zig"); @@ -101,45 +102,46 @@ export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize, switch (@as(AsyncCause, @enumFromInt(cause.num))) { .supervisor_software => w.print("Hart {d}: Software interrupt\r\n", .{hart_id}) catch while (true) {}, .supervisor_timer => { - time.interruptInSeconds(null, 1) catch while (true) {}; - schedule() catch while (true) {}; + time.interruptInSeconds(null, 1) catch |err| { + std.debug.panic("Hart {d}: Unable to set interrupt timer: {any}", .{ hart_id, err }); + }; + schedule() catch |err| { + std.debug.panic("Hart {d}: Unable to schedule next process: {any}", .{ hart_id, err }); + }; }, .supervisor_external => { const context: u14 = @intCast(2 * hart_id + 1); - const external_cause = plic.default.claim(context) catch while (true) {}; + const external_cause = plic.default.claim(context) catch |err| { + std.debug.panic("Hart {d}: Unable to claim external interrupt: {any}", .{ hart_id, err }); + }; if (external_cause) |source| { w.print("Hart {d}: External interrupt: 0x{x}\r\n", .{ hart_id, source }) catch while (true) {}; handleExternal(source); - plic.default.complete(context, source) catch while (true) {}; + plic.default.complete(context, source) catch |err| { + std.debug.panic("Hart {d}: Unable to complete external interrupt: {any}", .{ hart_id, err }); + }; } }, else => { - w.print("Hart {d}: Unhandled asynchronous interrupt: {d}\r\n", .{ hart_id, cause.num }) catch while (true) {}; - while (true) {} + std.debug.panic("Hart {d}: Unhandled asynchronous interrupt: {d}", .{ hart_id, cause.num }); }, } } else { switch (@as(SyncCause, @enumFromInt(cause.num))) { .illegal_instruction => { - w.print("Hart {d}: Illegal instruction\r\n", .{hart_id}) catch while (true) {}; - while (true) {} + std.debug.panic("Hart {d}: Illegal instruction, EPC = 0x{x:0>16}", .{ hart_id, epc }); }, .instruction_access_fault => { - w.print("Hart {d}: Instruction access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Instruction access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, .load_access_fault => { - w.print("Hart {d}: Load access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Load access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, .store_or_amo_access_fault => { - w.print("Hart {d}: Store/AMO access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Store/AMO access fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, .ecall => { - w.print("Hart {d}: Environment call from U-mode\r\n", .{hart_id}) catch while (true) {}; - syscall.handle(frame) catch |err| switch (err) { syscall.Error.UnknownSyscall => { const a0 = frame.general_purpose_registers[10]; @@ -150,20 +152,16 @@ export fn handleTrap(epc: usize, tval: usize, cause_bits: usize, hart_id: usize, return epc + 4; }, .instruction_page_fault => { - w.print("Hart {d}: Instruction page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Instruction page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, .load_page_fault => { - w.print("Hart {d}: Load page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Load page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, .store_or_amo_page_fault => { - w.print("Hart {d}: Store/AMO page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}\r\n", .{ hart_id, epc, tval }) catch while (true) {}; - return epc + 4; + std.debug.panic("Hart {d}: Store/AMO page fault: EPC = 0x{x:0>16}, TVAL = 0x{x:0>16}", .{ hart_id, epc, tval }); }, else => { - w.print("Hart {d}: Unhandled synchronous interrupt: {d}, EPC = 0x{x:0>16}\r\n", .{ hart_id, cause.num, epc }) catch while (true) {}; - while (true) {} + std.debug.panic("Hart {d}: Unhandled synchronous interrupt: {d}, EPC = 0x{x:0>16}", .{ hart_id, cause.num, epc }); }, } } |