From 9e5f060e45ef6b0d80a69697b021bd24672eed57 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 1 Apr 2014 20:09:13 +0200 Subject: lsxl: use 64bit for LBA48 to support 4 TB drives Cc: Prafulla Wadaskar Signed-off-by: Michael Walle --- include/configs/lsxl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 96a889fe87..97a8bb7aa3 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -161,6 +161,7 @@ #undef CONFIG_SYS_IDE_MAXDEVICE #define CONFIG_SYS_IDE_MAXDEVICE 1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_64BIT_LBA #endif #endif /* _CONFIG_LSXL_H */ -- cgit v1.2.3 From 848fe239c6b03556848e75676c27f0958009f4d7 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 1 Apr 2014 20:09:14 +0200 Subject: lsxl: rework boot scripts Move addresses for kernel, ramdisk and fdt blob to own variables. Add dtb blob loading to all existing boot scripts, dtb filenames were taken from vanilla kernel. Introduce new boot script bootcmd_legacy, which only loads a kernel and a ramdisk. Make this the default boot script. This should also restore the behaviour of the original bootloader. Cc: Prafulla Wadaskar Cc: Tom Rini Signed-off-by: Michael Walle --- include/configs/lsxl.h | 40 +++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 97a8bb7aa3..f5f49613c8 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -66,6 +66,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_USB +#define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION @@ -109,20 +110,41 @@ #define CONFIG_LOADADDR 0x00800000 #define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" + +#if defined(CONFIG_LSXHL) +#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" +#elif defined(CONFIG_LSCHLV2) +#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" +#else +#error "Unsupported board" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootsource=hdd\0" \ + "bootsource=legacy\0" \ "hdpart=0:1\0" \ - "bootcmd_net=bootp 0x00100000 uImage " \ - "&& tftpboot 0x00800000 uInitrd " \ + "kernel_addr=0x00800000\0" \ + "ramdisk_addr=0x01000000\0" \ + "fdt_addr=0x01ff0000\0" \ + "bootcmd_legacy=ide reset " \ + "&& load ide ${hdpart} 0x00100000 /uImage.buffalo " \ + "&& load ide ${hdpart} 0x00800000 /initrd.buffalo " \ "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_net=bootp ${kernel_addr} uImage " \ + "&& tftpboot ${ramdisk_addr} uInitrd " \ + "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_hdd=ide reset " \ - "&& ext2load ide ${hdpart} 0x00100000 /uImage " \ - "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load ide ${hdpart} ${kernel_addr} /uImage " \ + "&& load ide ${hdpart} ${ramdisk_addr} /uInitrd " \ + "&& load ide ${hdpart} ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_usb=usb start " \ - "&& fatload usb 0:1 0x00100000 /uImage " \ - "&& fatload usb 0:1 0x00800000 /uInitrd " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load usb 0:1 ${kernel_addr} /uImage " \ + "&& load usb 0:1 ${ramdisk_addr} /uInitrd " \ + "&& load usb 0:1 ${fdt_addr} " \ + "/" CONFIG_FDTFILE " " \ + "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ "eraseenv=sf probe 0 " \ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ -- cgit v1.2.3 From 46e09e6d1eb32a90705d162411476f57fff13860 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 11 Apr 2014 15:09:44 -0500 Subject: ARM: highbank: convert to generic board Enable CONFIG_SYS_GENERIC_BOARD on highbank. Signed-off-by: Rob Herring --- include/configs/highbank.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index a6202cfab4..da1c837cc7 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -13,6 +13,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT -- cgit v1.2.3 From cba69eeeaa67d3fb93ec6f3abab1f653abf895a9 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 5 May 2014 11:52:26 +0100 Subject: sunxi: add sun7i cpu, board and start of day support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson Signed-off-by: Aleksei Mamlin Signed-off-by: Alexandru Gagniuc Signed-off-by: Chen-Yu Tsai Signed-off-by: Emilio López Signed-off-by: Hans de Goede Signed-off-by: Henrik Nordstrom Signed-off-by: Jens Kuske Signed-off-by: Luc Verhaegen Signed-off-by: Luke Leighton Signed-off-by: Oliver Schinagl Signed-off-by: Patrick Wood Signed-off-by: Stefan Roese Signed-off-by: Wills Wang Signed-off-by: Ian Campbell Reviewed-by: Marek Vasut Cc: Tom Cubie Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/sunxi/Makefile | 11 +++ arch/arm/cpu/armv7/sunxi/board.c | 88 +++++++++++++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 19 ++++ arch/arm/cpu/armv7/sunxi/start.c | 1 + arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 77 +++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 122 ++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/spl.h | 20 ++++ board/sunxi/Makefile | 11 +++ board/sunxi/board.c | 57 +++++++++++ include/configs/sun7i.h | 24 +++++ include/configs/sunxi-common.h | 141 ++++++++++++++++++++++++++++ 12 files changed, 572 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/sunxi/board.c create mode 100644 arch/arm/cpu/armv7/sunxi/cpu_info.c create mode 100644 arch/arm/cpu/armv7/sunxi/start.c create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h create mode 100644 arch/arm/include/asm/arch-sunxi/spl.h create mode 100644 board/sunxi/Makefile create mode 100644 board/sunxi/board.c create mode 100644 include/configs/sun7i.h create mode 100644 include/configs/sunxi-common.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ab869b1ee8..232118d7f4 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index d81d26cf50..a64bfa18e0 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -8,7 +8,18 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-y += timer.o +obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN7I) += clock_sun4i.o + +ifndef CONFIG_SPL_BUILD +obj-y += cpu_info.o +endif + +ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SUN7I) += dram.o +ifdef CONFIG_SPL_FEL +obj-y += start.o +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c new file mode 100644 index 0000000000..b5c0cb7487 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Some init for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#ifdef CONFIG_SPL_BUILD +#include +#endif +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD +/* Pointer to the global data structure for SPL */ +DECLARE_GLOBAL_DATA_PTR; + +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nand flash, mmc2. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller + */ +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +/* No confirmation data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} +#endif + +int gpio_init(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(23), 1); + + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +/* do some early init */ +void s_init(void) +{ +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #1 << 6\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + + clock_init(); + timer_init(); + gpio_init(); + +#ifdef CONFIG_SPL_BUILD + gd = &gdata; + preloader_console_init(); + + sunxi_board_init(); +#endif +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c new file mode 100644 index 0000000000..b4c3d5c6dd --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + puts("CPU: Allwinner A20 (SUN7I)\n"); + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c new file mode 100644 index 0000000000..6b392fa835 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start.c @@ -0,0 +1 @@ +/* Intentionally empty. Only needed to get FEL SPL link line right */ diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds new file mode 100644 index 0000000000..364e35c32f --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2013 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(s_init) +SECTIONS +{ + . = 0x00002000; + + . = ALIGN(4); + .text : + { + *(.text.s_init) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + . = .; + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(4); + .note.gnu.build-id : + { + *(.note.gnu.build-id) + } + _end = .; + + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note*) } +} diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 0000000000..a987e51d57 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#define SUNXI_TVE0_BASE 0x01c0a000 +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#define SUNXI_SS_BASE 0x01c15000 +#define SUNXI_HDMI_BASE 0x01c16000 +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#define SUNXI_SPDIF_BASE 0x01c21000 +#define SUNXI_AC97_BASE 0x01c21400 +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 +#define SUNXI_SID_BASE 0x01c23800 +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 +#define SUNXI_CPUCFG_BASE 0x01c25c00 + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#define SUNXI_DE_FE0_BASE 0x01e00000 +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h new file mode 100644 index 0000000000..ff871bcaee --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -0,0 +1,20 @@ +/* + * This is a copy of omap3/spl.h: + * + * (C) Copyright 2012 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_SPL_H_ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_MMC2 5 /*emmc*/ +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_XIPWAIT 7 +#define BOOT_DEVICE_MMC2_2 0xff +#endif diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile new file mode 100644 index 0000000000..559112ebbd --- /dev/null +++ b/board/sunxi/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2012 Henrik Nordstrom +# +# Based on some other board Makefile +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += board.o diff --git a/board/sunxi/board.c b/board/sunxi/board.c new file mode 100644 index 0000000000..328334ab02 --- /dev/null +++ b/board/sunxi/board.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Some board init for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* add board specific code here */ +int board_init(void) +{ + int id_pfr1; + + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); + + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); + debug("id_pfr1: 0x%08x\n", id_pfr1); + /* Generic Timer Extension available? */ + if ((id_pfr1 >> 16) & 0xf) { + debug("Setting CNTFRQ\n"); + /* CNTFRQ == 24 MHz */ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + } + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + unsigned long ramsize; + + printf("DRAM:"); + ramsize = sunxi_dram_init(); + printf(" %lu MiB\n", ramsize >> 20); + if (!ramsize) + hang(); +} +#endif diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h new file mode 100644 index 0000000000..9b693f7039 --- /dev/null +++ b/include/configs/sun7i.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * (C) Copyright 2013 Luke Kenneth Casson Leighton + * + * Configuration settings for the Allwinner A20 (sun7i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A20 specific configuration + */ +#define CONFIG_SUN7I /* sun7i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun7i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h new file mode 100644 index 0000000000..3f7e314a8b --- /dev/null +++ b/include/configs/sunxi-common.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2012-2012 Henrik Nordstrom + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Configuration settings for the Allwinner sunxi series of boards. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_COMMON_CONFIG_H +#define _SUNXI_COMMON_CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUNXI /* sunxi family */ + +#include /* get chip and board defs */ + +#define CONFIG_SYS_TEXT_BASE 0x4a000000 + +/* + * Display CPU information + */ +#define CONFIG_DISPLAY_CPUINFO + +/* Serial & console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* ns16550 reg in the low bits of cpu reg */ +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 24000000 +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SETEXPR + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* 4MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_CMD_ECHO +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_GENERIC_BOARD + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */ + +/* standalone support */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000 + +#define CONFIG_SYS_HZ 1000 + +/* baudrate */ +#define CONFIG_BAUDRATE 115200 + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ + +/* FLASH and environment organization */ + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ +#define CONFIG_IDENT_STRING " Allwinner Technology" + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#define CONFIG_SYS_BOOT_GET_CMDLINE + +#include + +#define CONFIG_FAT_WRITE /* enable write access */ + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#define CONFIG_SPL +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" +#define CONFIG_SPL_TEXT_BASE 0x2000 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ +/* end of 32 KiB in sram */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_CONS_INDEX 1 /* UART0 */ + +#if !defined CONFIG_ENV_IS_IN_MMC && \ + !defined CONFIG_ENV_IS_IN_NAND && \ + !defined CONFIG_ENV_IS_IN_FAT && \ + !defined CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#ifndef CONFIG_SPL_BUILD +#include +#endif + +#endif /* _SUNXI_COMMON_CONFIG_H */ -- cgit v1.2.3 From 5835823da3a357468bc90c2b74bad3193555b918 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 5 May 2014 11:52:28 +0100 Subject: sunxi: add gmac Ethernet support Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i) processors. Enable for the Cubietruck. Signed-off-by: Chen-Yu Tsai Signed-off-by: Jens Kuske Signed-off-by: Ian Campbell Reviewed-by: Marek Vasut Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/sunxi/board.c | 23 +++++++++++++++++++++++ board/sunxi/Makefile | 1 + board/sunxi/gmac.c | 32 ++++++++++++++++++++++++++++++++ boards.cfg | 2 +- include/configs/sunxi-common.h | 17 +++++++++++++++++ include/netdev.h | 1 + 6 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 board/sunxi/gmac.c (limited to 'include') diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index b5c0cb7487..49c94489ee 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -11,6 +11,8 @@ */ #include +#include +#include #include #ifdef CONFIG_SPL_BUILD #include @@ -86,3 +88,24 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifdef CONFIG_CMD_NET +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + int rc; + +#ifdef CONFIG_SUNXI_GMAC + rc = sunxi_gmac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize gmac\n"); + return rc; + } +#endif + + return 0; +} +#endif diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 18b1e11733..cbf8f086a9 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -9,4 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-y += board.o +obj-$(CONFIG_SUNXI_GMAC) += gmac.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c new file mode 100644 index 0000000000..e48328d9e8 --- /dev/null +++ b/board/sunxi/gmac.c @@ -0,0 +1,32 @@ +#include +#include +#include +#include +#include +#include +#include + +int sunxi_gmac_initialize(bd_t *bis) +{ + int pin; + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set up clock gating */ + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); + + /* Set MII clock */ + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + + /* Configure pin mux settings for GMAC */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { + /* skip unused pins in RGMII mode */ + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) + continue; + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); + sunxi_gpio_set_drv(pin, 3); + } + + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +} diff --git a/boards.cfg b/boards.cfg index db3a6aef75..bc0503048f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,7 +379,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL - +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 3f7e314a8b..e844110d7a 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -127,6 +127,23 @@ #define CONFIG_CONS_INDEX 1 /* UART0 */ +#ifdef CONFIG_SUNXI_GMAC +#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_PHYLIB +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_DNS +#define CONFIG_NETCONSOLE +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#endif + #if !defined CONFIG_ENV_IS_IN_MMC && \ !defined CONFIG_ENV_IS_IN_NAND && \ !defined CONFIG_ENV_IS_IN_FAT && \ diff --git a/include/netdev.h b/include/netdev.h index e211f1841f..63481eca22 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,6 +78,7 @@ int sh_eth_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc91111_initialize(u8 dev_num, int base_addr); int smc911x_initialize(u8 dev_num, int base_addr); +int sunxi_gmac_initialize(bd_t *bis); int sunxi_wemac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); -- cgit v1.2.3 From e24ea55c04a8ee9c273dd879edda23bbde3d807a Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 5 May 2014 14:42:31 +0100 Subject: sunxi: mmc support On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote: > > + case 1: > > +#if CONFIG_MMC1_PG > Are you sure that this is correct and shouldn't be: > > +#ifdef CONFIG_MMC1_PG > > ? It's "correct" in so far as it works (the boards.cfg config stuff #defines things to 1), but I think you are right that it isn't the preferred style. But... > A quick scan through this patch series shows that this define > is not set at all. Perhaps its outdated? Or is it used to support > some other sunxi SoC? Not sure, perhaps it should be removed for > now. ...I had thought that it was to support some other board which wasn't being upstreamed right now, so eventually useful and harmless for now, but I've just checked and it isn't actually used by any of the boards in u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it. Rather than resend the entire series, here is v5.1 of this patch. > Other than this please add my: > > Reviewed-by: Stefan Roese Thanks! 8<--------------------------------- >From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 7 Mar 2014 04:29:39 +0000 Subject: [PATCH v5.1 7/8] sunxi: mmc support This adds support for the MMC controller on the Allwinner A20 (sun7i) processor. Signed-off-by: Henrik Nordstrom Signed-off-by: Luke Leighton Signed-off-by: Oliver Schinagl Signed-off-by: Wills Wang Signed-off-by: Ian Campbell Reviewed-by: Marek Vasut Reviewed-by: Stefan Roese Cc: Tom Cubie Cc: Aaron Maoye Cc: Pantelis Antoniou Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-sunxi/mmc.h | 124 +++++++++ board/sunxi/board.c | 63 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/sunxi_mmc.c | 503 ++++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 11 + 5 files changed, 702 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h create mode 100644 drivers/mmc/sunxi_mmc.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 0000000000..53196e3b02 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Aaron + * + * MMC register definition for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +#include + +struct sunxi_mmc { + u32 gctrl; /* 0x00 global control */ + u32 clkcr; /* 0x04 clock control */ + u32 timeout; /* 0x08 time out */ + u32 width; /* 0x0c bus width */ + u32 blksz; /* 0x10 block size */ + u32 bytecnt; /* 0x14 byte count */ + u32 cmd; /* 0x18 command */ + u32 arg; /* 0x1c argument */ + u32 resp0; /* 0x20 response 0 */ + u32 resp1; /* 0x24 response 1 */ + u32 resp2; /* 0x28 response 2 */ + u32 resp3; /* 0x2c response 3 */ + u32 imask; /* 0x30 interrupt mask */ + u32 mint; /* 0x34 masked interrupt status */ + u32 rint; /* 0x38 raw interrupt status */ + u32 status; /* 0x3c status */ + u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ + u32 funcsel; /* 0x44 function select */ + u32 cbcr; /* 0x48 CIU byte count */ + u32 bbcr; /* 0x4c BIU byte count */ + u32 dbgc; /* 0x50 debug enable */ + u32 res0[11]; + u32 dmac; /* 0x80 internal DMA control */ + u32 dlba; /* 0x84 internal DMA descr list base address */ + u32 idst; /* 0x88 internal DMA status */ + u32 idie; /* 0x8c internal DMA interrupt enable */ + u32 chda; /* 0x90 */ + u32 cbda; /* 0x94 */ + u32 res1[26]; + u32 fifo; /* 0x100 FIFO access address */ +}; + +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) + +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ + SUNXI_MMC_GCTRL_FIFO_RESET|\ + SUNXI_MMC_GCTRL_DMA_RESET) +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) + +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +#define SUNXI_MMC_CMD_START (0x1 << 31) + +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ + (SUNXI_MMC_RINT_RESP_ERROR | \ + SUNXI_MMC_RINT_RESP_CRC_ERROR | \ + SUNXI_MMC_RINT_DATA_CRC_ERROR | \ + SUNXI_MMC_RINT_RESP_TIMEOUT | \ + SUNXI_MMC_RINT_DATA_TIMEOUT | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ + SUNXI_MMC_RINT_START_BIT_ERROR | \ + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ + SUNXI_MMC_RINT_DATA_OVER | \ + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) + +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) + +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + +int sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 328334ab02..b05d0b9b18 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +45,67 @@ int dram_init(void) return 0; } +#ifdef CONFIG_GENERIC_MMC +static void mmc_pinmux_setup(int sdc) +{ + unsigned int pin; + + switch (sdc) { + case 0: + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: + /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 2: + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 3: + /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + default: + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); + break; + } +} + +int board_mmc_init(bd_t *bis) +{ + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA) + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif + + return 0; +} +#endif + #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 4c6ab9e05b..34febf52f0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 0000000000..eb7b1158d6 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,503 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Aaron + * + * MMC driver for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +struct sunxi_mmc_des { + u32 reserved1_1:1; + u32 dic:1; /* disable interrupt on completion */ + u32 last_des:1; /* 1-this data buffer is the last buffer */ + u32 first_des:1; /* 1-data buffer is the first buffer, + 0-data buffer contained in the next + descriptor is 1st buffer */ + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the + next descriptor address */ + u32 end_of_ring:1; /* 1-last descriptor flag when using dual + data buffer in descriptor */ + u32 reserved1_2:24; + u32 card_err_sum:1; /* transfer error flag */ + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ +#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:16; + u32 data_buf2_sz:16; + u32 buf_addr_ptr1; + u32 buf_addr_ptr2; +}; + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned database; + unsigned fatal_err; + unsigned mod_clk; + struct sunxi_mmc *reg; + struct mmc_config cfg; +}; + +/* support 4 mmc hosts */ +struct sunxi_mmc_host mmc_host[4]; + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->database = (unsigned int)mmchost->reg + 0x100; + mmchost->mmc_no = sdc_no; + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + unsigned int pll_clk; + unsigned int divider; + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d clock and io\n", sdc_no); + + /* config ahb clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); + + /* config mod clock */ + pll_clk = clock_get_pll6(); + /* should be close to 100 MHz but no more, so round up */ + divider = ((pll_clk + 99999999) / 100000000) - 1; + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider, + mmchost->mclkreg); + mmchost->mod_clk = pll_clk / (divider + 1); + + return 0; +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmd; + unsigned timeout_msecs = 2000; + + cmd = SUNXI_MMC_CMD_START | + SUNXI_MMC_CMD_UPCLK_ONLY | + SUNXI_MMC_CMD_WAIT_PRE_OVER; + writel(cmd, &mmchost->reg->cmd); + while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + /* clock update sets various irq status bits, clear these */ + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc, unsigned div) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* Disable Clock */ + rval &= ~SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Change Divider Factor */ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + rval |= div; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + /* Re-enable Clock */ + rval |= SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int clkdiv = 0; + + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n", + mmc->bus_width, mmc->clock, mmchost->mod_clk); + + /* Change clock first */ + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2; + if (mmc->clock) { + if (mmc_config_clock(mmc, clkdiv)) { + mmchost->fatal_err = 1; + return; + } + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(0x2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(0x1, &mmchost->reg->width); + else + writel(0x0, &mmchost->reg->width); +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + const int reading = !!(data->flags & MMC_DATA_READ); + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : + SUNXI_MMC_STATUS_FIFO_FULL; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned timeout_msecs = 2000; + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); + + for (i = 0; i < (byte_cnt >> 2); i++) { + while (readl(&mmchost->reg->status) & status_bit) { + if (!timeout_msecs--) + return -1; + udelay(1000); + } + + if (reading) + buff[i] = readl(mmchost->database); + else + writel(buff[i], mmchost->database); + } + + return 0; +} + +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned char *buff; + unsigned des_idx = 0; + unsigned buff_frag_num = + (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT; + unsigned remain; + unsigned i, rval; + ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num); + + buff = data->flags & MMC_DATA_READ ? + (unsigned char *)data->dest : (unsigned char *)data->src; + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); + + flush_cache((unsigned long)buff, (unsigned long)byte_cnt); + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */ + else + pdes[des_idx].data_buf1_sz = remain; + + pdes[des_idx].buf_addr_ptr1 = + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0) + pdes[des_idx].first_des = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_des = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; + } + } + flush_cache((unsigned long)pdes, + sizeof(struct sunxi_mmc_des) * (des_idx + 1)); + + rval = readl(&mmchost->reg->gctrl); + /* Enable DMA */ + writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + /* Reset iDMA */ + writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac); + /* Enable iDMA */ + writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE, + &mmchost->reg->dmac); + rval = readl(&mmchost->reg->idie) & + ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ); + if (data->flags & MMC_DATA_WRITE) + rval |= SUNXI_MMC_IDIE_TXIRQ; + else + rval |= SUNXI_MMC_IDIE_RXIRQ; + writel(rval, &mmchost->reg->idie); + writel((u32) pdes, &mmchost->reg->dlba); + writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3), + &mmchost->reg->ftrglevel); + + return 0; +} + +static void mmc_enable_dma_accesses(struct mmc *mmc, int dma) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + + unsigned int gctrl = readl(&mmchost->reg->gctrl); + if (dma) + gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + else + gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + writel(gctrl, &mmchost->reg->gctrl); +} + +static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, + unsigned int done_bit, const char *what) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int status; + + do { + status = readl(&mmchost->reg->rint); + if (!timeout_msecs-- || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return TIMEOUT; + } + udelay(1000); + } while (!(status & done_bit)); + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = mmc->priv; + unsigned int cmdval = SUNXI_MMC_CMD_START; + unsigned int timeout_msecs; + int error = 0; + unsigned int status = 0; + unsigned int usedma = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + if (!cmd->cmdidx) + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) + cmdval |= SUNXI_MMC_CMD_WRITE; + if (data->blocks > 1) + cmdval |= SUNXI_MMC_CMD_AUTO_STOP; + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) + if (bytecnt > 64) { +#else + if (0) { +#endif + usedma = 1; + mmc_enable_dma_accesses(mmc, 1); + ret = mmc_trans_data_by_dma(mmc, data); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + } else { + mmc_enable_dma_accesses(mmc, 0); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + } + if (ret) { + error = readl(&mmchost->reg->rint) & \ + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; + error = TIMEOUT; + goto out; + } + } + + error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); + if (error) + goto out; + + if (data) { + timeout_msecs = usedma ? 120 * bytecnt : 120; + debug("cacl timeout %x msec\n", timeout_msecs); + error = mmc_rint_wait(mmc, timeout_msecs, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, + "data"); + if (error) + goto out; + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout_msecs = 2000; + do { + status = readl(&mmchost->reg->status); + if (!timeout_msecs--) { + debug("busy timeout\n"); + error = TIMEOUT; + goto out; + } + udelay(1000); + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (data && usedma) { + /* IDMASTAREG + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = readl(&mmchost->reg->idst); + writel(status, &mmchost->reg->idst); + writel(0, &mmchost->reg->idie); + writel(0, &mmchost->reg->dmac); + writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + } + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, + &mmchost->reg->gctrl); + + return error; +} + +static const struct mmc_ops sunxi_mmc_ops = { + .send_cmd = mmc_send_cmd, + .set_ios = mmc_set_ios, + .init = mmc_core_init, +}; + +int sunxi_mmc_init(int sdc_no) +{ + struct mmc_config *cfg = &mmc_host[sdc_no].cfg; + + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + + cfg->name = "SUNXI SD/MMC"; + cfg->ops = &sunxi_mmc_ops; + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->host_caps = MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + + mmc_resource_init(sdc_no); + mmc_clk_io_on(sdc_no); + + if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL) + return -1; + + return 0; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e844110d7a..42534521d6 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -59,6 +59,16 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG +/* mmc config */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 +#define CONFIG_MMC_SUNXI_USE_DMA +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ + /* 4MB of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) @@ -94,6 +104,7 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ #define CONFIG_IDENT_STRING " Allwinner Technology" +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.2.3 From 50827a5991bb345319bd0ce76f5e2402fac0c391 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 5 May 2014 11:52:30 +0100 Subject: sunxi: non-FEL SPL boot support for sun7i MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for booting from an MMC card. Signed-off-by: Stefan Roese Signed-off-by: Henrik Nordström Signed-off-by: Ian Campbell Reviewed-by: Marek Vasut Cc: Tom Cubie Reviewed-by: Tom Rini --- Makefile | 10 +++ arch/arm/cpu/armv7/sunxi/config.mk | 8 ++ arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 52 ++++++++++++ boards.cfg | 1 + include/configs/sunxi-common.h | 26 ++++++ spl/Makefile | 13 +++ tools/.gitignore | 1 + tools/Makefile | 2 + tools/mksunxiboot.c | 142 ++++++++++++++++++++++++++++++++ 9 files changed, 255 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/config.mk create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds create mode 100644 tools/mksunxiboot.c (limited to 'include') diff --git a/Makefile b/Makefile index 928a8808b6..966fd14844 100644 --- a/Makefile +++ b/Makefile @@ -937,6 +937,13 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) +ifneq ($(CONFIG_SUNXI),) +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE + $(call if_changed,pad_cat) +endif + ifneq ($(CONFIG_TEGRA),) OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE @@ -1163,6 +1170,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl spl/u-boot-spl: tools prepare $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all +spl/sunxi-spl.bin: spl/u-boot-spl + @: + tpl/u-boot-tpl.bin: tools prepare $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk new file mode 100644 index 0000000000..00f5ffc683 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -0,0 +1,8 @@ +# Build a combined spl + u-boot image +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SPL_FEL +ALL-y += u-boot-sunxi-with-spl.bin +endif +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds new file mode 100644 index 0000000000..5008028aae --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram +} diff --git a/boards.cfg b/boards.cfg index bc0503048f..8b1177c36e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 42534521d6..5d72d62f14 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -17,6 +17,11 @@ * High Level Configuration Options */ #define CONFIG_SUNXI /* sunxi family */ +#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SPL_FEL +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ +#endif +#endif #include /* get chip and board defs */ @@ -121,11 +126,32 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT +#ifdef CONFIG_SPL_FEL + #define CONFIG_SPL #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" #define CONFIG_SPL_TEXT_BASE 0x2000 #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ + +#else /* CONFIG_SPL */ + +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ + +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ + +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ + +#endif /* CONFIG_SPL */ + /* end of 32 KiB in sram */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK diff --git a/spl/Makefile b/spl/Makefile index 55500fd897..bfb7c8aec8 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -189,6 +189,12 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin endif +ifdef CONFIG_SUNXI +ifndef CONFIG_SPL_FEL +ALL-y += $(obj)/sunxi-spl.bin +endif +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG @@ -216,6 +222,13 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif +ifdef CONFIG_SUNXI +quiet_cmd_mksunxiboot = MKSUNXI $@ +cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@ +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin + $(call if_changed,mksunxiboot) +endif + quiet_cmd_u-boot-spl = LD $@ cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \ diff --git a/tools/.gitignore b/tools/.gitignore index b1e997fc3e..725db906e8 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -11,6 +11,7 @@ /mkexynosspl /mpc86x_clk /mxsboot +/mksunxiboot /ncb /proftool /relocate-rela diff --git a/tools/Makefile b/tools/Makefile index 6e43a0150d..b64522440d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -131,6 +131,8 @@ hostprogs-$(CONFIG_MX23) += mxsboot$(SFX) hostprogs-$(CONFIG_MX28) += mxsboot$(SFX) HOSTCFLAGS_mxsboot$(SFX).o := -pedantic +hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX) + hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX) hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c new file mode 100644 index 0000000000..da7c9f0ddc --- /dev/null +++ b/tools/mksunxiboot.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * a simple tool to generate bootable image for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t b_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* + * We use a simplified header, only filling in what is needed + * by the boot ROM. To be compatible with Allwinner tools we + * would need to implement the proper fields here instead of + * padding. + */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE 0x5F0A6C39 + +/* check sum functon from sun4i boot code */ +int gen_check_sum(struct boot_file_head *head_p) +{ + uint32_t length; + uint32_t *buf; + uint32_t loop; + uint32_t i; + uint32_t sum; + + length = head_p->length; + if ((length & 0x3) != 0) /* must 4-byte-aligned */ + return -1; + buf = (uint32_t *)head_p; + head_p->check_sum = STAMP_VALUE; /* fill stamp */ + loop = length >> 2; + + /* calculate the sum */ + for (i = 0, sum = 0; i < loop; i++) + sum += buf[i]; + + /* write back check sum */ + head_p->check_sum = sum; + + return 0; +} + +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) + +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define BLOCK_SIZE 512 + +struct boot_img { + struct boot_file_head header; + char code[SRAM_LOAD_MAX_SIZE]; + char pad[BLOCK_SIZE]; +}; + +int main(int argc, char *argv[]) +{ + int fd_in, fd_out; + struct boot_img img; + unsigned file_size, load_size; + int count; + + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " \ + "bootable image.\n" \ + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = open(argv[1], O_RDONLY); + if (fd_in < 0) { + perror("Open input file"); + return EXIT_FAILURE; + } + + memset(img.pad, 0, BLOCK_SIZE); + + /* get input file size */ + file_size = lseek(fd_in, 0, SEEK_END); + + if (file_size > SRAM_LOAD_MAX_SIZE) { + fprintf(stderr, "ERROR: File too large!\n"); + return EXIT_FAILURE; + } else { + load_size = ALIGN(file_size, sizeof(int)); + } + + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); + if (fd_out < 0) { + perror("Open output file"); + return EXIT_FAILURE; + } + + /* read file to buffer to calculate checksum */ + lseek(fd_in, 0, SEEK_SET); + count = read(fd_in, img.code, load_size); + if (count != load_size) { + perror("Reading input image"); + return EXIT_FAILURE; + } + + /* fill the header */ + img.header.b_instruction = /* b instruction */ + 0xEA000000 | /* jump to the first instr after the header */ + ((sizeof(struct boot_file_head) / sizeof(int) - 2) + & 0x00FFFFFF); + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ + img.header.length = + ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE); + gen_check_sum(&img.header); + + count = write(fd_out, &img, img.header.length); + if (count != img.header.length) { + perror("Writing output"); + return EXIT_FAILURE; + } + + close(fd_in); + close(fd_out); + + return EXIT_SUCCESS; +} -- cgit v1.2.3 From cd23aac4bf978970bea3f460e0b55315c94c1fee Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 19 Mar 2014 14:48:45 +0800 Subject: ARM: atmel: enable SPL on sama5d3_xplained board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It supports boot from NAND and SD/MMC card. Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 87 +++++++++++++++++++++++++ include/configs/sama5d3_xplained.h | 50 ++++++++++++++ 2 files changed, 137 insertions(+) (limited to 'include') diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 39f2dc6475..92ed4e81d3 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -17,6 +17,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -128,3 +131,87 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d3_xplained_mci0_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d3_xplained_nand_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ENRDM_ON | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + /* + * As the DDR2-SDRAm device requires a refresh time is 7.8125us + * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks + */ + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(43) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x3 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_MDIV_4 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 41c946d1ec..e826e2dbd2 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -20,7 +20,11 @@ #define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT +#endif + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO @@ -74,8 +78,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x310000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif /* NAND flash */ #define CONFIG_CMD_NAND @@ -199,4 +207,46 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +/* SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#endif + #endif -- cgit v1.2.3 From 525049d3477af67e23dfd17dcb6cb66b34924536 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 24 Apr 2014 11:42:13 +0800 Subject: ARM: atmel: sama5d3xek: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following warning on boot: "Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed." Signed-off-by: Bo Shen Tested-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/sama5d3xek.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 516be85fe0..20a5f6e19e 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -34,6 +34,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_AT91_GPIO -- cgit v1.2.3 From 9652296ea3ba2e00f6b02b61248ed373d24d0b93 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 24 Apr 2014 11:42:14 +0800 Subject: ARM: atmel: sama5d3_xplained: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following warning on boot: "Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed." Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/sama5d3_xplained.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index e826e2dbd2..be6bb9366d 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -31,6 +31,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_AT91_GPIO -- cgit v1.2.3 From 68f164772e6caa11a71d394ee96ff1fd4d29c832 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 24 Apr 2014 11:42:15 +0800 Subject: ARM: atmel: at91sam9m10g45ek: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following warning on boot: "Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed." Signed-off-by: Bo Shen Tested-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9m10g45ek.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index ccfda71c95..7a3c9b524e 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -34,6 +34,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO -- cgit v1.2.3 From 495275925192edb0c5bd6cb1e3b6f85162ffd06b Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 24 Apr 2014 11:42:16 +0800 Subject: ARM: atmel: at91sam9x5ek: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable CONFIG_SYS_GENERIC_BOARD, so that we get rid of the following warning on boot: "Warning: Your board does not use generic board. Please read doc/README.generic-board and take action. Boards not upgraded by the late 2014 may break or be removed." Signed-off-by: Bo Shen Tested-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9x5ek.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index f0a6757ff6..5fc00af60b 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -30,6 +30,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO -- cgit v1.2.3 From ecd04611f6001901734b7c6e938fc9e36cbf930c Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 16 May 2014 10:51:05 +0200 Subject: corvus: remove unneeded CONFIG_AT91_LEGACY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Cc: Heiko Schocher --- include/configs/corvus.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 959e188d9a..631add3bd0 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_TEXT_BASE 0x73f00000 -#define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ -- cgit v1.2.3 From 7b1a411743db47648b2955c414a71836823acfd9 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 19 May 2014 14:23:39 +0200 Subject: mkimage: add atmelimage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new atmelimage converts a machine code BLOB to bootable ROM image. Atmel ROM has no sophisticated image format, it only checks the first 7 ARM vectors. The vectors can contain valid B or LDR opcodes, the 6'th vector contains the image size to load. Additionally the PMECC header can be written by the atmelimage target. The parameters must be given via the -n switch as a coma separated list. For example: mkimage -T atmelimage \ -n usePmecc=1,sectorPerPage=4,sectorSize=512,spareSize=64,eccBits=4,eccOffset=36 \ -d spl/u-boot-spl.bin boot.bin A provided image can be checked for correct header setup. It prints out the PMECC header parameters if it has one and the 6'th interrupt vector content. ---8<--- Image Type: ATMEL ROM-Boot Image with PMECC Header PMECC header ==================== eccOffset: 36 sectorSize: 512 eccBitReq: 4 spareSize: 64 nbSectorPerPage: 4 usePmecc: 1 ==================== 6'th vector has 17044 set --->8--- A SPL binary modified with the atmelimage mkimage target was succesfully booted on a sama5d34ek via MMC and NAND. Signed-off-by: Andreas Bießmann Cc: Bo Shen Cc: Heiko Schocher Tested-by: Bo Shen --- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 1 + tools/atmelimage.c | 342 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/imagetool.c | 2 + tools/imagetool.h | 1 + 6 files changed, 348 insertions(+) create mode 100644 tools/atmelimage.c (limited to 'include') diff --git a/common/image.c b/common/image.c index fa4864d24c..26eb89a2b2 100644 --- a/common/image.c +++ b/common/image.c @@ -139,6 +139,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, + { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 18861686cc..41e56abe15 100644 --- a/include/image.h +++ b/include/image.h @@ -225,6 +225,7 @@ struct lmb; #define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ #define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ +#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index b64522440d..e6d804596b 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -69,6 +69,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o rsa-verify.o rsa-checksum.o # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ + atmelimage.o \ $(FIT_SIG_OBJS-y) \ crc32.o \ default_image.o \ diff --git a/tools/atmelimage.c b/tools/atmelimage.c new file mode 100644 index 0000000000..c8101d2ddc --- /dev/null +++ b/tools/atmelimage.c @@ -0,0 +1,342 @@ +/* + * (C) Copyright 2014 + * Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include "mkimage.h" + +#include + +#define pr_err(fmt, args...) fprintf(stderr, "atmelimage Error: " fmt, ##args) + +static int atmel_check_image_type(uint8_t type) +{ + if (type == IH_TYPE_ATMELIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static uint32_t nand_pmecc_header[52]; + +/* + * A helper struct for parsing the mkimage -n parameter + * + * Keep in same order as the configs array! + */ +static struct pmecc_config { + int use_pmecc; + int sector_per_page; + int spare_size; + int ecc_bits; + int sector_size; + int ecc_offset; +} pmecc; + +/* + * Strings used for configure the PMECC header via -n mkimage switch + * + * We estimate a coma separated list of key=value pairs. The mkimage -n + * parameter argument should not contain any whitespace. + * + * Keep in same order as struct pmecc_config! + */ +static const char * const configs[] = { + "usePmecc", + "sectorPerPage", + "spareSize", + "eccBits", + "sectorSize", + "eccOffset" +}; + +static int atmel_find_pmecc_parameter_in_token(const char *token) +{ + size_t pos; + char *param; + + debug("token: '%s'\n", token); + + for (pos = 0; pos < ARRAY_SIZE(configs); pos++) { + if (strncmp(token, configs[pos], strlen(configs[pos])) == 0) { + param = strstr(token, "="); + if (!param) + goto err; + + param++; + debug("\t%s parameter: '%s'\n", configs[pos], param); + + switch (pos) { + case 0: + pmecc.use_pmecc = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 1: + pmecc.sector_per_page = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 2: + pmecc.spare_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 3: + pmecc.ecc_bits = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 4: + pmecc.sector_size = strtol(param, NULL, 10); + return EXIT_SUCCESS; + case 5: + pmecc.ecc_offset = strtol(param, NULL, 10); + return EXIT_SUCCESS; + } + } + } + +err: + pr_err("Could not find parameter in token '%s'\n", token); + return EXIT_FAILURE; +} + +static int atmel_parse_pmecc_params(char *txt) +{ + char *token; + + token = strtok(txt, ","); + while (token != NULL) { + if (atmel_find_pmecc_parameter_in_token(token)) + return EXIT_FAILURE; + + token = strtok(NULL, ","); + } + + return EXIT_SUCCESS; +} + +static int atmel_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + size_t size = image_size; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + ints += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + /* check the seven interrupt vectors of binary */ + for (pos = 0; pos < 7; pos++) { + debug("atmelimage: interrupt vector #%d is 0x%08X\n", pos+1, + ints[pos]); + /* + * all vectors except the 6'th one must contain valid + * LDR or B Opcode + */ + if (pos == 5) + /* 6'th vector has image size set, check later */ + continue; + if ((ints[pos] & 0xff000000) == 0xea000000) + /* valid B Opcode */ + continue; + if ((ints[pos] & 0xfffff000) == 0xe59ff000) + /* valid LDR (I=0, P=1, U=1, B=0, W=0, L=1) */ + continue; + /* ouch, one of the checks has missed ... */ + return 1; + } + + return ints[5] != cpu_to_le32(size); +} + +static void atmel_print_pmecc_header(const uint32_t word) +{ + int val; + + printf("\t\tPMECC header\n"); + + printf("\t\t====================\n"); + + val = (word >> 18) & 0x1ff; + printf("\t\teccOffset: %9i\n", val); + + val = (((word >> 16) & 0x3) == 0) ? 512 : 1024; + printf("\t\tsectorSize: %8i\n", val); + + if (((word >> 13) & 0x7) <= 2) + val = (2 << ((word >> 13) & 0x7)); + else + val = (12 << (((word >> 13) & 0x7) - 3)); + printf("\t\teccBitReq: %9i\n", val); + + val = (word >> 4) & 0x1ff; + printf("\t\tspareSize: %9i\n", val); + + val = (1 << ((word >> 1) & 0x3)); + printf("\t\tnbSectorPerPage: %3i\n", val); + + printf("\t\tusePmecc: %10i\n", word & 0x1); + printf("\t\t====================\n"); +} + +static void atmel_print_header(const void *ptr) +{ + uint32_t *ints = (uint32_t *)ptr; + size_t pos; + + /* check if we have an PMECC header attached */ + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + if (ints[pos] >> 28 != 0xC) + break; + + if (pos == ARRAY_SIZE(nand_pmecc_header)) { + printf("Image Type:\tATMEL ROM-Boot Image with PMECC Header\n"); + atmel_print_pmecc_header(ints[0]); + pos += 5; + } else { + printf("Image Type:\tATMEL ROM-Boot Image without PMECC Header\n"); + pos = 5; + } + printf("\t\t6'th vector has %u set\n", le32_to_cpu(ints[pos])); +} + +static void atmel_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + /* just save the image size into 6'th interrupt vector */ + uint32_t *ints = (uint32_t *)ptr; + size_t cnt; + size_t pos = 5; + size_t size = sbuf->st_size; + + for (cnt = 0; cnt < ARRAY_SIZE(nand_pmecc_header); cnt++) + if (ints[cnt] >> 28 != 0xC) + break; + + if (cnt == ARRAY_SIZE(nand_pmecc_header)) { + pos += ARRAY_SIZE(nand_pmecc_header); + size -= sizeof(nand_pmecc_header); + } + + ints[pos] = cpu_to_le32(size); +} + +static int atmel_check_params(struct image_tool_params *params) +{ + if (strlen(params->imagename) > 0) + if (atmel_parse_pmecc_params(params->imagename)) + return EXIT_FAILURE; + + return !(!params->eflag && + !params->fflag && + !params->xflag && + ((params->dflag && !params->lflag) || + (params->lflag && !params->dflag))); +} + +static int atmel_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + uint32_t tmp; + size_t pos; + + if (strlen(params->imagename) == 0) + return EXIT_SUCCESS; + + tmp = 0xC << 28; + + tmp |= (pmecc.ecc_offset & 0x1ff) << 18; + + switch (pmecc.sector_size) { + case 512: + tmp |= 0 << 16; + break; + case 1024: + tmp |= 1 << 16; + break; + + default: + pr_err("Wrong sectorSize (%i) for PMECC header\n", + pmecc.sector_size); + return EXIT_FAILURE; + } + + switch (pmecc.ecc_bits) { + case 2: + tmp |= 0 << 13; + break; + case 4: + tmp |= 1 << 13; + break; + case 8: + tmp |= 2 << 13; + break; + case 12: + tmp |= 3 << 13; + break; + case 24: + tmp |= 4 << 13; + break; + + default: + pr_err("Wrong eccBits (%i) for PMECC header\n", + pmecc.ecc_bits); + return EXIT_FAILURE; + } + + tmp |= (pmecc.spare_size & 0x1ff) << 4; + + switch (pmecc.sector_per_page) { + case 1: + tmp |= 0 << 1; + break; + case 2: + tmp |= 1 << 1; + break; + case 4: + tmp |= 2 << 1; + break; + case 8: + tmp |= 3 << 1; + break; + + default: + pr_err("Wrong sectorPerPage (%i) for PMECC header\n", + pmecc.sector_per_page); + return EXIT_FAILURE; + } + + if (pmecc.use_pmecc) + tmp |= 1; + + for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) + nand_pmecc_header[pos] = tmp; + + debug("PMECC header filled 52 times with 0x%08X\n", tmp); + + tparams->header_size = sizeof(nand_pmecc_header); + tparams->hdr = nand_pmecc_header; + + return EXIT_SUCCESS; +} + +static struct image_type_params atmelimage_params = { + .name = "ATMEL ROM-Boot Image support", + .header_size = 0, + .hdr = NULL, + .check_image_type = atmel_check_image_type, + .verify_header = atmel_verify_header, + .print_header = atmel_print_header, + .set_header = atmel_set_header, + .check_params = atmel_check_params, + .vrec_header = atmel_vrec_header, +}; + +void init_atmel_image_type(void) +{ + register_image_type(&atmelimage_params); +} diff --git a/tools/imagetool.c b/tools/imagetool.c index da72115e53..32d6278edb 100644 --- a/tools/imagetool.c +++ b/tools/imagetool.c @@ -27,6 +27,8 @@ void register_image_tool(imagetool_register_t image_register) */ register_func = image_register; + /* Init ATMEL ROM Boot Image generation/list support */ + init_atmel_image_type(); /* Init Freescale PBL Boot image generation/list support */ init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ diff --git a/tools/imagetool.h b/tools/imagetool.h index a3e9d302eb..c480687ec1 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -159,6 +159,7 @@ void register_image_type(struct image_type_params *tparams); * Supported image types init functions */ void init_default_image_type(void); +void init_atmel_image_type(void); void init_pbl_image_type(void); void init_ais_image_type(void); void init_kwb_image_type(void); -- cgit v1.2.3 From e166a8311ff29c020b6f17f133ada53e6f98befa Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 19 May 2014 14:23:41 +0200 Subject: sama5d3xek: enable PMECC header generation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Cc: Bo Shen Tested-by: Bo Shen --- include/configs/sama5d3xek.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 20a5f6e19e..fe63d80ed5 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -283,6 +283,7 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER #elif CONFIG_SYS_USE_SERIALFLASH #define CONFIG_SPL_SPI_SUPPORT -- cgit v1.2.3 From 7f6bd0da9b06afb534bc13ef02b15eb7a5f067e3 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 20 May 2014 17:44:44 +0800 Subject: at91: remove redundant AT91FAMILY definition in board config file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now the AT91FAMILY is already defined in the at91 SoC header. The at91 board config file will include the SoC header file. So we can remove the redundant AT91FAMILY definition in at91 board config files. Signed-off-by: Josh Wu [rebase patch] Signed-off-by: Andreas Bießmann --- include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/corvus.h | 2 -- include/configs/cpu9260.h | 1 - include/configs/ethernut5.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/vl_ma2sc.h | 1 - 9 files changed, 10 deletions(-) (limited to 'include') diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 7a3c9b524e..5d5fbe5853 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index e23549d444..ebfc26edaf 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_TEXT_BASE 0x26f00000 #define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 5fc00af60b..b1d4baaff9 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_AT91SAM9X5EK -#define CONFIG_AT91FAMILY #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 631add3bd0..6171060e9c 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -33,8 +33,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 39f7062388..1feaefd14e 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -32,7 +32,6 @@ #include -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 480d8678c6..89d668b7a5 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -24,7 +24,6 @@ /* CPU information */ #define CONFIG_ARM926EJS -#define CONFIG_AT91FAMILY #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index be6bb9366d..f72ab0bad0 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index fe63d80ed5..da2718044c 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 14c6e675c1..8e58adeb20 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -14,7 +14,6 @@ /*--------------------------------------------------------------------------*/ #define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ -#define CONFIG_AT91FAMILY #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ #define CONFIG_ARCH_CPU_INIT -- cgit v1.2.3 From e83c4d24b12266d5616429b60e1a15e04c507e89 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 20 May 2014 17:44:45 +0800 Subject: ARM: at91: remove redundant ARM926EJS definition in board config files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As at91 board config file will include the SoC header, so we can remove the ARM926EJS definition in board config files. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9n12ek.h | 2 -- include/configs/ethernut5.h | 1 - include/configs/vl_ma2sc.h | 1 - 3 files changed, 4 deletions(-) (limited to 'include') diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index ebfc26edaf..9b0e588c6b 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -18,8 +18,6 @@ #define CONFIG_SYS_TEXT_BASE 0x26f00000 -#define CONFIG_ARM926EJS - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 89d668b7a5..c81fc44b12 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -23,7 +23,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_ARM926EJS #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 8e58adeb20..bef821f337 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -13,7 +13,6 @@ /*--------------------------------------------------------------------------*/ -#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ #define CONFIG_ARCH_CPU_INIT -- cgit v1.2.3 From cf874c190e1796a77be6661cacc43aebb94c7a57 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 21 May 2014 10:42:15 +0800 Subject: ARM: at91sam9m10g45ek: enable mci0 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also we enable the mmc command in configuration file. As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION, so remove the redundant CONFIG_DOS_PARTITION definition. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 17 +++++++++++++++++ board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 10 ++++++++++ include/configs/at91sam9m10g45ek.h | 15 ++++++++++++++- 3 files changed, 41 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 7d7725c4b8..0e6c0da1bd 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -165,3 +165,20 @@ void at91_macb_hw_init(void) #endif } #endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void at91_mci_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ + + /* Enable clock */ + writel(1 << ATMEL_ID_MCI0, &pmc->pcer); +} +#endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index b7e2efd2fc..57881164c5 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -16,6 +16,7 @@ #include #include #include +#include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include #endif @@ -217,6 +218,15 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + int board_early_init_f(void) { at91_seriald_hw_init(); diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 5d5fbe5853..61f7bc2079 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -116,6 +116,20 @@ #endif +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* Ethernet */ #define CONFIG_MACB #define CONFIG_RMII @@ -127,7 +141,6 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 -#define CONFIG_DOS_PARTITION #define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -- cgit v1.2.3 From 9637a1bb896efe392a58dd2772e2c3fcb646409d Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 21 May 2014 10:42:16 +0800 Subject: ARM: at91sam9m10g45ek: add mmc environment configuration support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In this configuration the environment will save in file: uboot.env of mmc card. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- boards.cfg | 1 + include/configs/at91sam9m10g45ek.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index 8b1177c36e..866f51287b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -102,6 +102,7 @@ Active arm arm926ejs at91 atmel at91sam9263ek Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen +Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_mmc at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_MMC Bo Shen Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 61f7bc2079..341b21df27 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -148,6 +148,7 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 +#ifdef CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env in nandflash */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0xc0000 @@ -163,6 +164,24 @@ "256k(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "root=/dev/mtdblock7 rw rootfstype=jffs2" +#elif CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env + linux in mmc */ +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE 0 +#define FAT_ENV_PART 1 +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "mtdparts=atmel_nand:" \ + "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ + "root=/dev/mmcblk0p2 rw rootwait" +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ + "fatload mmc 0:1 0x72000000 zImage; " \ + "bootz 0x72000000 - 0x71000000" +#endif #define CONFIG_BAUDRATE 115200 -- cgit v1.2.3