From 1d7ad68559e2238d42730c7de0a3d5e159d72cdd Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 26 Sep 2021 00:54:44 +0200 Subject: arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- include/pci.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/pci.h') diff --git a/include/pci.h b/include/pci.h index 11009a2f78..797f224e2f 100644 --- a/include/pci.h +++ b/include/pci.h @@ -495,6 +495,10 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ +#define PCI_EXP_RTCTL 28 /* Root Control */ +#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ +#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ -- cgit v1.2.3