From 0c45c77b8aeac0c3c5a0b5ea13a44ee478b51fdb Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Fri, 15 Apr 2022 16:40:49 +0530 Subject: i.MX6SX: crypto/fsl: fix entropy delay value RNG Hardware error is reported due to incorrect entropy delay rng self test are run to determine the correct ent_dly. test is executed with different voltage and temperature to identify the worst case value for ent_dly. after adding a margin value(1000), ent_dly should be at least 12000. Signed-off-by: Gaurav Jain Reviewed-by: Fabio Estevam --- include/fsl_sec.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/fsl_sec.h') diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 7b6e3e2c20..d57c4ca820 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -48,7 +48,11 @@ struct rng4tst { u32 rtmctl; /* misc. control register */ u32 rtscmisc; /* statistical check misc. register */ u32 rtpkrrng; /* poker range register */ -#define RTSDCTL_ENT_DLY_MIN 3200 +#ifdef CONFIG_MX6SX +#define RTSDCTL_ENT_DLY 12000 +#else +#define RTSDCTL_ENT_DLY 3200 +#endif #define RTSDCTL_ENT_DLY_MAX 12800 union { u32 rtpkrmax; /* PRGM=1: poker max. limit register */ -- cgit v1.2.3