From 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 27 Mar 2014 17:54:47 -0700 Subject: driver/ddr/fsl: Add DDR4 support to Freescale DDR driver Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun --- include/fsl_ddr_sdram.h | 63 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 7 deletions(-) (limited to 'include/fsl_ddr_sdram.h') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 2a36431146..e39b716188 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,11 +13,13 @@ * Pick a basic DDR Technology. */ #include +#include -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 +#define SDRAM_TYPE_DDR4 5 #define DDR_BL4 4 /* burst length 4 */ #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ @@ -54,6 +56,12 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #ifndef CONFIG_FSL_SDRAM_TYPE #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#elif defined(CONFIG_SYS_FSL_DDR4) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 +#endif #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ #define FSL_DDR_ODT_NEVER 0x0 @@ -116,7 +124,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define TIMING_CFG_2_CPO_MASK 0x0F800000 -#if defined(CONFIG_P4080) +#if defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) #define RD_TO_PRE_MASK 0xf #define RD_TO_PRE_SHIFT 13 #define WR_DATA_DELAY_MASK 0xf @@ -154,9 +163,27 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define DDR_CDR2_ODT_MASK 0x1 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) +#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#ifdef CONFIG_SYS_FSL_DDR3L +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_200ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x5 +#define DDR_CDR_ODT_46ohm 0x7 +#elif defined(CONFIG_SYS_FSL_DDR4) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_100ohm 0x1 +#define DDR_CDR_ODT_120OHM 0x2 +#define DDR_CDR_ODT_80ohm 0x3 +#define DDR_CDR_ODT_60ohm 0x4 +#define DDR_CDR_ODT_40ohm 0x5 +#define DDR_CDR_ODT_50ohm 0x6 +#define DDR_CDR_ODT_30ohm 0x7 +#else #define DDR_CDR_ODT_OFF 0x0 #define DDR_CDR_ODT_120ohm 0x1 #define DDR_CDR_ODT_180ohm 0x2 @@ -165,6 +192,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define DDR_CDR_ODT_60hm 0x5 #define DDR_CDR_ODT_70ohm 0x6 #define DDR_CDR_ODT_47ohm 0x7 +#endif /* DDR3L */ #else #define DDR_CDR_ODT_75ohm 0x0 #define DDR_CDR_ODT_55ohm 0x1 @@ -188,6 +216,7 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_2; unsigned int ddr_sdram_cfg; unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_cfg_3; unsigned int ddr_sdram_mode; unsigned int ddr_sdram_mode_2; unsigned int ddr_sdram_mode_3; @@ -196,6 +225,14 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sdram_mode_6; unsigned int ddr_sdram_mode_7; unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_mode_9; + unsigned int ddr_sdram_mode_10; + unsigned int ddr_sdram_mode_11; + unsigned int ddr_sdram_mode_12; + unsigned int ddr_sdram_mode_13; + unsigned int ddr_sdram_mode_14; + unsigned int ddr_sdram_mode_15; + unsigned int ddr_sdram_mode_16; unsigned int ddr_sdram_md_cntl; unsigned int ddr_sdram_interval; unsigned int ddr_data_init; @@ -204,6 +241,10 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_init_ext_addr; unsigned int timing_cfg_4; unsigned int timing_cfg_5; + unsigned int timing_cfg_6; + unsigned int timing_cfg_7; + unsigned int timing_cfg_8; + unsigned int timing_cfg_9; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; unsigned int ddr_wrlvl_cntl_2; @@ -211,6 +252,14 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; + unsigned int ddr_sdram_rcw_3; + unsigned int ddr_sdram_rcw_4; + unsigned int ddr_sdram_rcw_5; + unsigned int ddr_sdram_rcw_6; + unsigned int dq_map_0; + unsigned int dq_map_1; + unsigned int dq_map_2; + unsigned int dq_map_3; unsigned int ddr_eor; unsigned int ddr_cdr1; unsigned int ddr_cdr2; @@ -225,7 +274,7 @@ typedef struct memctl_options_partial_s { unsigned int all_dimms_burst_lengths_bitmask; unsigned int all_dimms_registered; unsigned int all_dimms_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ + /* unsigned int lowest_common_spd_caslat; */ unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; -- cgit v1.2.3 From aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 17 Apr 2014 15:33:46 +0800 Subject: mpc85xx/t104x: Add deep sleep framework support When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- README | 4 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++ arch/powerpc/lib/board.c | 16 ++++++++++++ drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 52 ++++++++++++++++++++++++++++++++++--- include/fsl_ddr_sdram.h | 4 +++ 5 files changed, 80 insertions(+), 4 deletions(-) (limited to 'include/fsl_ddr_sdram.h') diff --git a/README b/README index bbd7399f53..017a13df4d 100644 --- a/README +++ b/README @@ -431,6 +431,10 @@ The following options need to be configured: This CONFIG is defined when the CPC is configured as SRAM at the time of U-boot entry and is required to be re-initialized. + CONFIG_DEEP_SLEEP + Inidcates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 941c20e00a..867abb6cf7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,6 +350,7 @@ void cpu_init_f (void) extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -414,6 +415,13 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index f86c6f3e8f..8b03d3aa07 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -343,6 +343,13 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif +#ifdef CONFIG_DEEP_SLEEP + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + u32 start_addr; + typedef void (*func_t)(void); + func_t kernel_resume; +#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -360,6 +367,15 @@ void board_init_f(ulong bootflag) if ((*init_fnc_ptr) () != 0) hang(); +#ifdef CONFIG_DEEP_SLEEP + /* Jump to kernel in deep sleep case */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { + start_addr = in_be32(&scfg->sparecr[1]); + kernel_resume = (func_t)start_addr; + kernel_resume(); + } +#endif + #ifdef CONFIG_POST post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(NULL)); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index c805086416..4d5572ef21 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -15,6 +15,7 @@ #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #endif +DECLARE_GLOBAL_DATA_PTR; /* * regs has the to-be-set values for DDR controller registers @@ -43,6 +44,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 save1, save2; #endif +#ifdef CONFIG_DEEP_SLEEP + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool sleep_flag = 0; +#endif + +#ifdef CONFIG_DEEP_SLEEP + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + sleep_flag = 1; +#endif + switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -119,7 +130,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + out_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + else +#endif + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -132,8 +149,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) { + out_be32(&ddr->init_addr, 0); + out_be32(&ddr->init_ext_addr, (1 << 31)); + } else +#endif + { + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + } out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); @@ -374,8 +399,22 @@ step2: udelay(500); asm volatile("sync;isync"); +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) { + /* enter self-refresh */ + setbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + /* do board specific memory setup */ + board_mem_sleep_setup(); + } +#endif + /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + else +#endif + temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); @@ -526,4 +565,9 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ +#ifdef CONFIG_DEEP_SLEEP + if (sleep_flag) + /* exit self-refresh */ + clrbits_be32(&ddr->sdram_cfg_2, (1 << 31)); +#endif } diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e39b716188..e8a2db91cb 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -406,6 +406,10 @@ static int __board_need_mem_reset(void) int board_need_mem_reset(void) __attribute__((weak, alias("__board_need_mem_reset"))); +void __weak board_mem_sleep_setup(void) +{ +} + /* * The 85xx boards have a common prototype for fixed_sdram so put the * declaration here. -- cgit v1.2.3