From 2c1e11dd52e7d1db79b33e3e4c2fded573b70a9d Mon Sep 17 00:00:00 2001
From: Andy Yan <andy.yan@rock-chips.com>
Date: Thu, 1 Jun 2017 18:00:55 +0800
Subject: rockchip: Add core Soc start-up code for rv1108

RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core
from Rockchip. It is designed for varies application scenario such
as car DVR, sports DV, secure camera and UAV camera.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 drivers/sysreset/sysreset_rv1108.c | 46 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_rv1108.c

(limited to 'drivers/sysreset/sysreset_rv1108.c')

diff --git a/drivers/sysreset/sysreset_rv1108.c b/drivers/sysreset/sysreset_rv1108.c
new file mode 100644
index 0000000000..9d8e9f7ade
--- /dev/null
+++ b/drivers/sysreset/sysreset_rv1108.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rv1108.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct rv1108_cru *cru = rockchip_get_cru();
+
+	if (IS_ERR(cru))
+		return PTR_ERR(cru);
+
+	switch (type) {
+	case SYSRESET_WARM:
+		writel(0xeca8, &cru->glb_srst_snd_val);
+		break;
+	case SYSRESET_COLD:
+		writel(0xfdb9, &cru->glb_srst_fst_val);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops rv1108_sysreset = {
+	.request	= rv1108_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rv1108) = {
+	.name	= "rv1108_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rv1108_sysreset,
+};
-- 
cgit v1.2.3