From a5e770b21ccc4d3ffc5cf50cab481cb0e35ee6ce Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Wed, 23 Nov 2022 02:04:51 -0700 Subject: spi: zynqmp_gqspi: Update tapdelay value The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1 based on the recommended value in IP spec. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi/zynqmp_gqspi.c') diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 48eff777df..83a5c8aebf 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -94,7 +94,7 @@ #define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 -#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 #define GQSPI_USE_DATA_DLY 0x1 -- cgit v1.2.3 From 906e20a613abdcba5f558ac8e93cb6fad464f786 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 25 Nov 2022 16:14:13 +0530 Subject: spi: zynqmp_qspi: Add support for 64-bit read/write When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/spi/zynqmp_gqspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/spi/zynqmp_gqspi.c') diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 83a5c8aebf..335b458cb9 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -662,7 +662,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { - u32 addr; + unsigned long addr; u32 size; u32 actuallen = priv->len; u32 totallen = priv->len; @@ -678,7 +678,9 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, totallen -= priv->len; /* Save remaining bytes length to read */ actuallen = priv->len; /* Actual number of bytes reading */ - writel((unsigned long)buf, &dma_regs->dmadst); + writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst); + writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0), + &dma_regs->dmadstmsb); writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); addr = (unsigned long)buf; -- cgit v1.2.3