From ccdabd8956936319c5f7112bf5774e839b085874 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:35 -0700 Subject: spi: Correct operations check in dm_spi_xfer() At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index fbb58c783e..a4e4ad55c6 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -493,13 +493,6 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } -static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - printf("ICH SPI: Only supports memory operations\n"); - return -1; -} - static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -612,7 +605,7 @@ static const struct spi_controller_mem_ops ich_controller_mem_ops = { }; static const struct dm_spi_ops ich_spi_ops = { - .xfer = ich_spi_xfer, + /* xfer is not supported */ .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, -- cgit v1.2.3 From 674990c0dc21ecedaddb1f923455027bd489914c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:37 -0700 Subject: spi: ich: Move init function just above probe() It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 122 +++++++++++++++++++++++++++--------------------------- 1 file changed, 61 insertions(+), 61 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index a4e4ad55c6..3eb4599ba2 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -112,67 +112,6 @@ static int ich9_can_do_33mhz(struct udevice *dev) return speed == 1; } -static int ich_init_controller(struct udevice *dev, - struct ich_spi_platdata *plat, - struct ich_spi_priv *ctlr) -{ - ulong sbase_addr; - void *sbase; - - /* SBASE is similar */ - pch_get_spi_base(dev->parent, &sbase_addr); - sbase = (void *)sbase_addr; - debug("%s: sbase=%p\n", __func__, sbase); - - if (plat->ich_version == ICHV_7) { - struct ich7_spi_regs *ich7_spi = sbase; - - ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich7_spi->opmenu); - ctlr->optype = offsetof(struct ich7_spi_regs, optype); - ctlr->addr = offsetof(struct ich7_spi_regs, spia); - ctlr->data = offsetof(struct ich7_spi_regs, spid); - ctlr->databytes = sizeof(ich7_spi->spid); - ctlr->status = offsetof(struct ich7_spi_regs, spis); - ctlr->control = offsetof(struct ich7_spi_regs, spic); - ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); - ctlr->preop = offsetof(struct ich7_spi_regs, preop); - ctlr->base = ich7_spi; - } else if (plat->ich_version == ICHV_9) { - struct ich9_spi_regs *ich9_spi = sbase; - - ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich9_spi->opmenu); - ctlr->optype = offsetof(struct ich9_spi_regs, optype); - ctlr->addr = offsetof(struct ich9_spi_regs, faddr); - ctlr->data = offsetof(struct ich9_spi_regs, fdata); - ctlr->databytes = sizeof(ich9_spi->fdata); - ctlr->status = offsetof(struct ich9_spi_regs, ssfs); - ctlr->control = offsetof(struct ich9_spi_regs, ssfc); - ctlr->speed = ctlr->control + 2; - ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); - ctlr->preop = offsetof(struct ich9_spi_regs, preop); - ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); - ctlr->pr = &ich9_spi->pr[0]; - ctlr->base = ich9_spi; - } else { - debug("ICH SPI: Unrecognised ICH version %d\n", - plat->ich_version); - return -EINVAL; - } - - /* Work out the maximum speed we can support */ - ctlr->max_speed = 20000000; - if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) - ctlr->max_speed = 33000000; - debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", - plat->ich_version, ctlr->base, ctlr->max_speed); - - ich_set_bbar(ctlr, 0); - - return 0; -} - static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) { if (plat->ich_version == ICHV_7) { @@ -493,6 +432,67 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } +static int ich_init_controller(struct udevice *dev, + struct ich_spi_platdata *plat, + struct ich_spi_priv *ctlr) +{ + ulong sbase_addr; + void *sbase; + + /* SBASE is similar */ + pch_get_spi_base(dev->parent, &sbase_addr); + sbase = (void *)sbase_addr; + debug("%s: sbase=%p\n", __func__, sbase); + + if (plat->ich_version == ICHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; + + ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich7_spi->opmenu); + ctlr->optype = offsetof(struct ich7_spi_regs, optype); + ctlr->addr = offsetof(struct ich7_spi_regs, spia); + ctlr->data = offsetof(struct ich7_spi_regs, spid); + ctlr->databytes = sizeof(ich7_spi->spid); + ctlr->status = offsetof(struct ich7_spi_regs, spis); + ctlr->control = offsetof(struct ich7_spi_regs, spic); + ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); + ctlr->preop = offsetof(struct ich7_spi_regs, preop); + ctlr->base = ich7_spi; + } else if (plat->ich_version == ICHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; + + ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich9_spi->opmenu); + ctlr->optype = offsetof(struct ich9_spi_regs, optype); + ctlr->addr = offsetof(struct ich9_spi_regs, faddr); + ctlr->data = offsetof(struct ich9_spi_regs, fdata); + ctlr->databytes = sizeof(ich9_spi->fdata); + ctlr->status = offsetof(struct ich9_spi_regs, ssfs); + ctlr->control = offsetof(struct ich9_spi_regs, ssfc); + ctlr->speed = ctlr->control + 2; + ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); + ctlr->preop = offsetof(struct ich9_spi_regs, preop); + ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); + ctlr->pr = &ich9_spi->pr[0]; + ctlr->base = ich9_spi; + } else { + debug("ICH SPI: Unrecognised ICH version %d\n", + plat->ich_version); + return -EINVAL; + } + + /* Work out the maximum speed we can support */ + ctlr->max_speed = 20000000; + if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) + ctlr->max_speed = 33000000; + debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", + plat->ich_version, ctlr->base, ctlr->max_speed); + + ich_set_bbar(ctlr, 0); + + return 0; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); -- cgit v1.2.3 From 17e754492ffd3e308763f2543c9b8e4f85fac2f1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:38 -0700 Subject: spi: ich: Move the protection/lockdown code into a function Reduce the size of the probe function but putting this code into its own function. Also remove the assumption that the PCH is always a parent of the SPI controller, as this is not the case APL platforms. Use driver model to find the PCH instead. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 63 +++++++++++++++++++++++++++++++++++++------------------ drivers/spi/ich.h | 1 + 2 files changed, 44 insertions(+), 20 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 3eb4599ba2..4d61be02ec 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -98,13 +98,14 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) /* @return 1 if the SPI flash supports the 33MHz speed */ static int ich9_can_do_33mhz(struct udevice *dev) { + struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; /* Observe SPI Descriptor Component Section 0 */ - dm_pci_write_config32(dev->parent, 0xb0, 0x1000); + dm_pci_write_config32(priv->pch, 0xb0, 0x1000); /* Extract the Write/Erase SPI Frequency from descriptor */ - dm_pci_read_config32(dev->parent, 0xb4, &fdod); + dm_pci_read_config32(priv->pch, 0xb4, &fdod); /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ speed = (fdod >> 21) & 7; @@ -432,6 +433,37 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; } +static int ich_protect_lockdown(struct udevice *dev) +{ + struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); + int ret = -ENOSYS; + + /* Disable the BIOS write protect so write commands are allowed */ + if (priv->pch) + ret = pch_set_spi_protect(priv->pch, false); + if (ret == -ENOSYS) { + u8 bios_cntl; + + bios_cntl = ich_readb(priv, priv->bcr); + bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ + bios_cntl |= 1; /* Write Protect Disable (WPD) */ + ich_writeb(priv, bios_cntl, priv->bcr); + } else if (ret) { + debug("%s: Failed to disable write-protect: err=%d\n", + __func__, ret); + return ret; + } + + /* Lock down SPI controller settings if required */ + if (plat->lockdown) { + ich_spi_config_opcode(dev); + spi_lock_down(plat, priv->base); + } + + return 0; +} + static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) @@ -497,30 +529,15 @@ static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); struct ich_spi_priv *priv = dev_get_priv(dev); - uint8_t bios_cntl; int ret; ret = ich_init_controller(dev, plat, priv); if (ret) return ret; - /* Disable the BIOS write protect so write commands are allowed */ - ret = pch_set_spi_protect(dev->parent, false); - if (ret == -ENOSYS) { - bios_cntl = ich_readb(priv, priv->bcr); - bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ - bios_cntl |= 1; /* Write Protect Disable (WPD) */ - ich_writeb(priv, bios_cntl, priv->bcr); - } else if (ret) { - debug("%s: Failed to disable write-protect: err=%d\n", - __func__, ret); - return ret; - } - /* Lock down SPI controller settings if required */ - if (plat->lockdown) { - ich_spi_config_opcode(dev); - spi_lock_down(plat, priv->base); - } + ret = ich_protect_lockdown(dev); + if (ret) + return ret; priv->cur_speed = priv->max_speed; @@ -579,9 +596,15 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); int node = dev_of_offset(dev); int ret; + /* Find a PCH if there is one */ + uclass_first_device(UCLASS_PCH, &priv->pch); + if (!priv->pch) + priv->pch = dev_get_parent(dev); + ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); if (ret == 0) { plat->ich_version = ICHV_7; diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 3dfb2aaff1..77057878a5 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -191,6 +191,7 @@ struct ich_spi_priv { ulong max_speed; /* Maximum bus speed in MHz */ ulong cur_speed; /* Current bus speed */ struct spi_trans trans; /* current transaction in progress */ + struct udevice *pch; /* PCH, used to control SPI access */ }; #endif /* _ICH_H_ */ -- cgit v1.2.3 From 702b28a163ea8f6b80c9a850e8884a66bd059727 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:39 -0700 Subject: spi: ich: Convert to livetree Use dev_get_driver_data() to obtain the device type. It has the same effect and is shorter. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 4d61be02ec..6460144560 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -597,28 +597,16 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); struct ich_spi_priv *priv = dev_get_priv(dev); - int node = dev_of_offset(dev); - int ret; /* Find a PCH if there is one */ uclass_first_device(UCLASS_PCH, &priv->pch); if (!priv->pch) priv->pch = dev_get_parent(dev); - ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); - if (ret == 0) { - plat->ich_version = ICHV_7; - } else { - ret = fdt_node_check_compatible(gd->fdt_blob, node, - "intel,ich9-spi"); - if (ret == 0) - plat->ich_version = ICHV_9; - } + plat->ich_version = dev_get_driver_data(dev); + plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node, - "intel,spi-lock-down"); - - return ret; + return 0; } static const struct spi_controller_mem_ops ich_controller_mem_ops = { @@ -639,8 +627,8 @@ static const struct dm_spi_ops ich_spi_ops = { }; static const struct udevice_id ich_spi_ids[] = { - { .compatible = "intel,ich7-spi" }, - { .compatible = "intel,ich9-spi" }, + { .compatible = "intel,ich7-spi", ICHV_7 }, + { .compatible = "intel,ich9-spi", ICHV_9 }, { } }; -- cgit v1.2.3 From b47aa26eb91d74fc78a6aa4e57cc2f4641b42e94 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:40 -0700 Subject: spi: ich: Fix header order Move the header files into the right order. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 6460144560..eeb4c274b8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -13,9 +14,8 @@ #include #include #include -#include #include -#include +#include #include "ich.h" -- cgit v1.2.3 From a550662c270eb66b373498dae0cea2456fb30e22 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:41 -0700 Subject: spi: ich: Various small tidy-ups Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index eeb4c274b8..b83dfb854d 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -5,6 +5,8 @@ * This file is derived from the flashrom project. */ +#define LOG_CATEGORY UCLASS_SPI + #include #include #include @@ -19,8 +21,6 @@ #include "ich.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef DEBUG_TRACE #define debug_trace(fmt, args...) debug(fmt, ##args) #else @@ -96,7 +96,7 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) } /* @return 1 if the SPI flash supports the 33MHz speed */ -static int ich9_can_do_33mhz(struct udevice *dev) +static bool ich9_can_do_33mhz(struct udevice *dev) { struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; @@ -173,8 +173,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, } if (opcode_index == ctlr->menubytes) { - printf("ICH SPI: Opcode %x not found\n", - trans->opcode); + debug("ICH SPI: Opcode %x not found\n", trans->opcode); return -EINVAL; } @@ -182,8 +181,8 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, optype = (optypes >> (opcode_index * 2)) & 0x3; if (optype != trans->type) { - printf("ICH SPI: Transaction doesn't fit type %d\n", - optype); + debug("ICH SPI: Transaction doesn't fit type %d\n", + optype); return -ENOSPC; } return opcode_index; @@ -214,9 +213,9 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, } udelay(10); } + debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n", + status, bitmask, wait_til_set, status & bitmask); - printf("ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); return -ETIMEDOUT; } -- cgit v1.2.3 From 75214b051bfbbdafa5134b4320b9e4ae6ee9b22d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:42 -0700 Subject: spi: ich: Add mmio_base to struct ich_spi_platdata It is useful to store the mmio base in platdata. It reduces the amount of casting needed. Update the code and move the struct to the C file at the same time, as we will need to use with of-platdata. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 27 +++++++++++++-------------- drivers/spi/ich.h | 5 ----- 2 files changed, 13 insertions(+), 19 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index b83dfb854d..08c37ca4ab 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -27,6 +27,12 @@ #define debug_trace(x, args...) #endif +struct ich_spi_platdata { + enum ich_version ich_version; /* Controller version, 7 or 9 */ + bool lockdown; /* lock down controller settings? */ + ulong mmio_base; /* Base of MMIO registers */ +}; + static u8 ich_readb(struct ich_spi_priv *priv, int reg) { u8 value = readb(priv->base + reg); @@ -467,16 +473,9 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { - ulong sbase_addr; - void *sbase; - - /* SBASE is similar */ - pch_get_spi_base(dev->parent, &sbase_addr); - sbase = (void *)sbase_addr; - debug("%s: sbase=%p\n", __func__, sbase); - + ctlr->base = (void *)plat->mmio_base; if (plat->ich_version == ICHV_7) { - struct ich7_spi_regs *ich7_spi = sbase; + struct ich7_spi_regs *ich7_spi = ctlr->base; ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); @@ -488,9 +487,8 @@ static int ich_init_controller(struct udevice *dev, ctlr->control = offsetof(struct ich7_spi_regs, spic); ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); ctlr->preop = offsetof(struct ich7_spi_regs, preop); - ctlr->base = ich7_spi; } else if (plat->ich_version == ICHV_9) { - struct ich9_spi_regs *ich9_spi = sbase; + struct ich9_spi_regs *ich9_spi = ctlr->base; ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); @@ -505,7 +503,6 @@ static int ich_init_controller(struct udevice *dev, ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; - ctlr->base = ich9_spi; } else { debug("ICH SPI: Unrecognised ICH version %d\n", plat->ich_version); @@ -516,8 +513,8 @@ static int ich_init_controller(struct udevice *dev, ctlr->max_speed = 20000000; if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) ctlr->max_speed = 33000000; - debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", - plat->ich_version, ctlr->base, ctlr->max_speed); + debug("ICH SPI: Version ID %d detected at %lx, speed %ld\n", + plat->ich_version, plat->mmio_base, ctlr->max_speed); ich_set_bbar(ctlr, 0); @@ -605,6 +602,8 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); + pch_get_spi_base(priv->pch, &plat->mmio_base); + return 0; } diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 77057878a5..623b2c547a 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -168,11 +168,6 @@ enum ich_version { ICHV_9, }; -struct ich_spi_platdata { - enum ich_version ich_version; /* Controller version, 7 or 9 */ - bool lockdown; /* lock down controller settings? */ -}; - struct ich_spi_priv { int opmenu; int menubytes; -- cgit v1.2.3 From 43c145b8b3eeb77a31d3dd4810929b14c29003de Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:44 -0700 Subject: spi: ich: Correct max-size bug in ich_spi_adjust_size() This incorrectly shortens read operations if there is a maximum write size but no maximum read size. Fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 08c37ca4ab..17b7a0ba0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -425,9 +425,11 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) page_offset = do_div(aux, ICH_BOUNDARY); } - if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) { - op->data.nbytes = min(ICH_BOUNDARY - page_offset, - slave->max_read_size); + if (op->data.dir == SPI_MEM_DATA_IN) { + if (slave->max_read_size) { + op->data.nbytes = min(ICH_BOUNDARY - page_offset, + slave->max_read_size); + } } else if (slave->max_write_size) { op->data.nbytes = min(ICH_BOUNDARY - page_offset, slave->max_write_size); -- cgit v1.2.3 From 0d3ee3e199650d0bd43aca5e85080997f5772d3c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:45 -0700 Subject: spi: ich: Support of-platdata for fast-spi The Intel Fast SPI interface is similar to ICH. Add of-platdata support for this using the "intel,fast-spi" compatible string. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 17b7a0ba0b..7d66b900c8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -28,9 +29,13 @@ #endif struct ich_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_fast_spi dtplat; +#endif enum ich_version ich_version; /* Controller version, 7 or 9 */ bool lockdown; /* lock down controller settings? */ ulong mmio_base; /* Base of MMIO registers */ + pci_dev_t bdf; /* PCI address used by of-platdata */ }; static u8 ich_readb(struct ich_spi_priv *priv, int reg) @@ -594,6 +599,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ich_spi_priv *priv = dev_get_priv(dev); /* Find a PCH if there is one */ @@ -603,8 +610,13 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); +#else + plat->ich_version = ICHV_APL; + plat->mmio_base = plat->dtplat.early_regs[0]; + plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base); return 0; } @@ -632,8 +644,8 @@ static const struct udevice_id ich_spi_ids[] = { { } }; -U_BOOT_DRIVER(ich_spi) = { - .name = "ich_spi", +U_BOOT_DRIVER(intel_fast_spi) = { + .name = "intel_fast_spi", .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops, -- cgit v1.2.3 From 1facebd18fd7369e7629bce1d4fe78d5432fd773 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:46 -0700 Subject: spi: ich: Support hardware sequencing Apollo Lake (APL) only supports hardware sequencing. Add support for this into the SPI driver, as an option. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 209 +++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/spi/ich.h | 39 ++++++++++ 2 files changed, 245 insertions(+), 3 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 7d66b900c8..db895a396d 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include "ich.h" @@ -36,6 +38,7 @@ struct ich_spi_platdata { bool lockdown; /* lock down controller settings? */ ulong mmio_base; /* Base of MMIO registers */ pci_dev_t bdf; /* PCI address used by of-platdata */ + bool hwseq; /* Use hardware sequencing (not s/w) */ }; static u8 ich_readb(struct ich_spi_priv *priv, int reg) @@ -245,7 +248,8 @@ static void ich_spi_config_opcode(struct udevice *dev) ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); } -static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +static int ich_spi_exec_op_swseq(struct spi_slave *slave, + const struct spi_mem_op *op) { struct udevice *bus = dev_get_parent(slave->dev); struct ich_spi_platdata *plat = dev_get_platdata(bus); @@ -416,6 +420,197 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return 0; } +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross page boundary. + */ +static uint get_xfer_len(u32 offset, int len, int page_size) +{ + uint xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + uint bytes_left = ALIGN(offset, page_size) - offset; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +/* Fill FDATAn FIFO in preparation for a write transaction */ +static void fill_xfer_fifo(struct fast_spi_regs *regs, const void *data, + uint len) +{ + memcpy(regs->fdata, data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data */ +static void drain_xfer_fifo(struct fast_spi_regs *regs, void *dest, uint len) +{ + memcpy(dest, regs->fdata, len); +} + +/* Fire up a transfer using the hardware sequencer */ +static void start_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle, + uint offset, uint len) +{ + /* Make sure all W1C status bits get cleared */ + u32 hsfsts; + + hsfsts = readl(®s->hsfsts_ctl); + hsfsts &= ~(HSFSTS_FCYCLE_MASK | HSFSTS_FDBC_MASK); + hsfsts |= HSFSTS_AEL | HSFSTS_FCERR | HSFSTS_FDONE; + + /* Set up transaction parameters */ + hsfsts |= hsfsts_cycle << HSFSTS_FCYCLE_SHIFT; + hsfsts |= ((len - 1) << HSFSTS_FDBC_SHIFT) & HSFSTS_FDBC_MASK; + hsfsts |= HSFSTS_FGO; + + writel(offset, ®s->faddr); + writel(hsfsts, ®s->hsfsts_ctl); +} + +static int wait_for_hwseq_xfer(struct fast_spi_regs *regs, uint offset) +{ + ulong start; + u32 hsfsts; + + start = get_timer(0); + do { + hsfsts = readl(®s->hsfsts_ctl); + if (hsfsts & HSFSTS_FCERR) { + debug("SPI transaction error at offset %x HSFSTS = %08x\n", + offset, hsfsts); + return -EIO; + } + if (hsfsts & HSFSTS_AEL) + return -EPERM; + + if (hsfsts & HSFSTS_FDONE) + return 0; + } while (get_timer(start) < SPIBAR_HWSEQ_XFER_TIMEOUT_MS); + + debug("SPI transaction timeout at offset %x HSFSTS = %08x, timer %d\n", + offset, hsfsts, (uint)get_timer(start)); + + return -ETIMEDOUT; +} + +/** + * exec_sync_hwseq_xfer() - Execute flash transfer by hardware sequencing + * + * This waits until complete or timeout + * + * @regs: SPI registers + * @hsfsts_cycle: Cycle type (enum hsfsts_cycle_t) + * @offset: Offset to access + * @len: Number of bytes to transfer (can be 0) + * @return 0 if OK, -EIO on flash-cycle error (FCERR), -EPERM on access error + * (AEL), -ETIMEDOUT on timeout + */ +static int exec_sync_hwseq_xfer(struct fast_spi_regs *regs, uint hsfsts_cycle, + uint offset, uint len) +{ + start_hwseq_xfer(regs, hsfsts_cycle, offset, len); + + return wait_for_hwseq_xfer(regs, offset); +} + +static int ich_spi_exec_op_hwseq(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct spi_flash *flash = dev_get_uclass_priv(slave->dev); + struct udevice *bus = dev_get_parent(slave->dev); + struct ich_spi_priv *priv = dev_get_priv(bus); + struct fast_spi_regs *regs = priv->base; + uint page_size; + uint offset; + int cycle; + uint len; + bool out; + int ret; + u8 *buf; + + offset = op->addr.val; + len = op->data.nbytes; + + switch (op->cmd.opcode) { + case SPINOR_OP_RDID: + cycle = HSFSTS_CYCLE_RDID; + break; + case SPINOR_OP_READ_FAST: + cycle = HSFSTS_CYCLE_READ; + break; + case SPINOR_OP_PP: + cycle = HSFSTS_CYCLE_WRITE; + break; + case SPINOR_OP_WREN: + /* Nothing needs to be done */ + return 0; + case SPINOR_OP_WRSR: + cycle = HSFSTS_CYCLE_WR_STATUS; + break; + case SPINOR_OP_RDSR: + cycle = HSFSTS_CYCLE_RD_STATUS; + break; + case SPINOR_OP_WRDI: + return 0; /* ignore */ + case SPINOR_OP_BE_4K: + cycle = HSFSTS_CYCLE_4K_ERASE; + while (len) { + uint xfer_len = 0x1000; + + ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); + if (ret) + return ret; + offset += xfer_len; + len -= xfer_len; + } + return 0; + default: + debug("Unknown cycle %x\n", op->cmd.opcode); + return -EINVAL; + }; + + out = op->data.dir == SPI_MEM_DATA_OUT; + buf = out ? (u8 *)op->data.buf.out : op->data.buf.in; + page_size = flash->page_size ? : 256; + + while (len) { + uint xfer_len = get_xfer_len(offset, len, page_size); + + if (out) + fill_xfer_fifo(regs, buf, xfer_len); + + ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len); + if (ret) + return ret; + + if (!out) + drain_xfer_fifo(regs, buf, xfer_len); + + offset += xfer_len; + buf += xfer_len; + len -= xfer_len; + } + + return 0; +} + +static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + struct udevice *bus = dev_get_parent(slave->dev); + struct ich_spi_platdata *plat = dev_get_platdata(bus); + int ret; + + bootstage_start(BOOTSTAGE_ID_ACCUM_SPI, "fast_spi"); + if (plat->hwseq) + ret = ich_spi_exec_op_hwseq(slave, op); + else + ret = ich_spi_exec_op_swseq(slave, op); + bootstage_accum(BOOTSTAGE_ID_ACCUM_SPI); + + return ret; +} + static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) { unsigned int page_offset; @@ -583,9 +778,11 @@ static int ich_spi_child_pre_probe(struct udevice *dev) /* * Yes this controller can only write a small number of bytes at - * once! The limit is typically 64 bytes. + * once! The limit is typically 64 bytes. For hardware sequencing a + * a loop is used to get around this. */ - slave->max_write_size = priv->databytes; + if (!plat->hwseq) + slave->max_write_size = priv->databytes; /* * ICH 7 SPI controller only supports array read command * and byte program command for SST flash @@ -611,10 +808,16 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); pch_get_spi_base(priv->pch, &plat->mmio_base); + /* + * Use an int so that the property is present in of-platdata even + * when false. + */ + plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0); #else plat->ich_version = ICHV_APL; plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); + plat->hwseq = plat->dtplat.intel_hardware_seq; #endif debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base); diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index 623b2c547a..c7cf37b932 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -163,6 +163,45 @@ struct spi_trans { #define ICH_BOUNDARY 0x1000 +#define HSFSTS_FDBC_SHIFT 24 +#define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT) +#define HSFSTS_WET BIT(21) +#define HSFSTS_FCYCLE_SHIFT 17 +#define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT) + +/* Supported flash cycle types */ +enum hsfsts_cycle_t { + HSFSTS_CYCLE_READ = 0, + HSFSTS_CYCLE_WRITE = 2, + HSFSTS_CYCLE_4K_ERASE, + HSFSTS_CYCLE_64K_ERASE, + HSFSTS_CYCLE_RDSFDP, + HSFSTS_CYCLE_RDID, + HSFSTS_CYCLE_WR_STATUS, + HSFSTS_CYCLE_RD_STATUS, +}; + +#define HSFSTS_FGO BIT(16) +#define HSFSTS_FLOCKDN BIT(15) +#define HSFSTS_FDV BIT(14) +#define HSFSTS_FDOPSS BIT(13) +#define HSFSTS_WRSDIS BIT(11) +#define HSFSTS_SAF_CE BIT(8) +#define HSFSTS_SAF_ACTIVE BIT(7) +#define HSFSTS_SAF_LE BIT(6) +#define HSFSTS_SCIP BIT(5) +#define HSFSTS_SAF_DLE BIT(4) +#define HSFSTS_SAF_ERROR BIT(3) +#define HSFSTS_AEL BIT(2) +#define HSFSTS_FCERR BIT(1) +#define HSFSTS_FDONE BIT(0) +#define HSFSTS_W1C_BITS 0xff + +/* Maximum bytes of data that can fit in FDATAn (0x10) registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000 + enum ich_version { ICHV_7, ICHV_9, -- cgit v1.2.3 From 92842147c3113e83462fcad00fa5cd343c4b945e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:47 -0700 Subject: spi: ich: Add support for get_mmap() method Add this method so that the memory-mapped location of the SPI flash can be queried. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index db895a396d..160ec370fd 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -611,6 +611,37 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; } +static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep, + uint *map_sizep, uint *offsetp) +{ + pci_dev_t spi_bdf; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct pci_child_platdata *pplat = dev_get_parent_platdata(bus); + + spi_bdf = pplat->devfn; +#else + struct ich_spi_platdata *plat = dev_get_platdata(bus); + + /* + * We cannot rely on plat->bdf being set up yet since this method can + * be called before the device is probed. Use the of-platdata directly + * instead. + */ + spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + + return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp); +} + +static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, + uint *offsetp) +{ + struct udevice *bus = dev_get_parent(dev); + + return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp); +} + static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) { unsigned int page_offset; @@ -835,6 +866,7 @@ static const struct dm_spi_ops ich_spi_ops = { .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, + .get_mmap = ich_get_mmap, /* * cs_info is not needed, since we require all chip selects to be * in the device tree explicitly -- cgit v1.2.3 From 636555a4c4c96607613a7013b4b8536b10b5e8e4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:48 -0700 Subject: spi: ich: Add TPL support In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 48 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 160ec370fd..0cd073c03c 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -19,8 +19,11 @@ #include #include #include +#include #include #include +#include +#include #include "ich.h" @@ -115,6 +118,8 @@ static bool ich9_can_do_33mhz(struct udevice *dev) struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; + if (!CONFIG_IS_ENABLED(PCI)) + return false; /* Observe SPI Descriptor Component Section 0 */ dm_pci_write_config32(priv->pch, 0xb0, 0x1000); @@ -706,6 +711,15 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { + if (spl_phase() == PHASE_TPL) { + struct ich_spi_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = fast_spi_early_init(plat->bdf, plat->mmio_base); + if (ret) + return ret; + } + ctlr->base = (void *)plat->mmio_base; if (plat->ich_version == ICHV_7) { struct ich7_spi_regs *ich7_spi = ctlr->base; @@ -754,6 +768,26 @@ static int ich_init_controller(struct udevice *dev, return 0; } +static int ich_cache_bios_region(struct udevice *dev) +{ + ulong map_base; + uint map_size; + uint offset; + ulong base; + int ret; + + ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset); + if (ret) + return ret; + + /* Don't use WRBACK since we are not supposed to write to SPI flash */ + base = SZ_4G - map_size; + mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size); + log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size); + + return 0; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -764,10 +798,16 @@ static int ich_spi_probe(struct udevice *dev) if (ret) return ret; - ret = ich_protect_lockdown(dev); - if (ret) - return ret; - + if (spl_phase() == PHASE_TPL) { + /* Cache the BIOS to speed things up */ + ret = ich_cache_bios_region(dev); + if (ret) + return ret; + } else { + ret = ich_protect_lockdown(dev); + if (ret) + return ret; + } priv->cur_speed = priv->max_speed; return 0; -- cgit v1.2.3 From 3937df3d6c0b88745399434c58d80960f7bf31af Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Dec 2019 21:42:49 -0700 Subject: spi: ich: Add Apollo Lake support Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/spi/ich.c | 19 ++++++++++++++----- drivers/spi/ich.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-) (limited to 'drivers/spi/ich.c') diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 0cd073c03c..133b25b72e 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -106,10 +106,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; - minaddr &= bbar_mask; - ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + if (ctlr->bbar) { + minaddr &= bbar_mask; + ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + } } /* @return 1 if the SPI flash supports the 33MHz speed */ @@ -750,6 +752,7 @@ static int ich_init_controller(struct udevice *dev, ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; + } else if (plat->ich_version == ICHV_APL) { } else { debug("ICH SPI: Unrecognised ICH version %d\n", plat->ich_version); @@ -878,7 +881,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); + if (plat->ich_version == ICHV_APL) { + plat->mmio_base = dm_pci_read_bar32(dev, 0); + } else { + /* SBASE is similar */ + pch_get_spi_base(priv->pch, &plat->mmio_base); + } /* * Use an int so that the property is present in of-platdata even * when false. @@ -916,6 +924,7 @@ static const struct dm_spi_ops ich_spi_ops = { static const struct udevice_id ich_spi_ids[] = { { .compatible = "intel,ich7-spi", ICHV_7 }, { .compatible = "intel,ich9-spi", ICHV_9 }, + { .compatible = "intel,fast-spi", ICHV_APL }, { } }; diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index c7cf37b932..d7f1ffdf37 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -205,6 +205,7 @@ enum hsfsts_cycle_t { enum ich_version { ICHV_7, ICHV_9, + ICHV_APL, }; struct ich_spi_priv { -- cgit v1.2.3