From b3c29dc9e5f0ed2bef4f20927a8c9bba4342a1cb Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 15 Nov 2021 15:32:30 +0100 Subject: stm32mp1: ram: remove tuning support Remove the DDR interactive command tuning, as the support of a predefined DDR PHY tuning is removed for STM32MP1 driver in SPL and in TF-A and the result of this tuning will be never used. Moreover this SW tuning procedure can failed on some hardware configuration (to many BIST errors and no convergence); it will be no more supported in the next delivery of the DDR utilities included in the CubeMX tool of STMicroelectronics. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/ram/stm32mp1/stm32mp1_ddr.c') diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 9d086601a4..4d78aa5cb1 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -557,7 +557,7 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) (u32)&phy->pgsr, pgsr, ret); } -void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) +static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) { pir |= DDRPHYC_PIR_INIT; writel(pir, &phy->pir); @@ -626,7 +626,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode) log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat); } -void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) +static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) { start_sw_done(ctl); /* quasi-dynamic register update*/ @@ -637,8 +637,8 @@ void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) wait_sw_done_ack(ctl); } -void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, - u32 rfshctl3, u32 pwrctl) +static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + u32 rfshctl3, u32 pwrctl) { start_sw_done(ctl); if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH)) -- cgit v1.2.3