From 1c848a258600490f6964597b92b69a107af141d6 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 8 May 2014 22:26:32 +0100 Subject: net/designware: ensure device private data is DMA aligned. struct dw_eth_dev contains fields which are accessed via DMA, so make sure it is aligned to a dma boundary. Without this I see: ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0 Signed-off-by: Ian Campbell Reviewed-by: Alexey Brodkin Acked-by: Marek Vasut --- drivers/net/designware.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 78751b2600..41ab3ac0b6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -414,7 +414,8 @@ int designware_initialize(ulong base_addr, u32 interface) * Since the priv structure contains the descriptors which need a strict * buswidth alignment, memalign is used to allocate memory */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; -- cgit v1.2.3 From 964ea7c1cea6228aa414f4aee5acf25bcd87ca21 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 8 May 2014 22:26:33 +0100 Subject: net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell Cc: Alexey Brodkin --- drivers/net/designware.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 41ab3ac0b6..fa816bf2f6 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -280,10 +280,18 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - /* Invalidate only "status" field for the following check */ - invalidate_dcache_range((unsigned long)&desc_p->txrx_status, - (unsigned long)&desc_p->txrx_status + - sizeof(desc_p->txrx_status)); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so roundup to + * ARCH_DMA_MINALIGN. This is safe because the individual + * descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN. + */ + invalidate_dcache_range( + (unsigned long)desc_p, + (unsigned long)desc_p + + roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN)); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -351,7 +359,7 @@ static int dw_eth_recv(struct eth_device *dev) /* Invalidate received data */ invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, (unsigned long)desc_p->dmamac_addr + - length); + roundup(length, ARCH_DMA_MINALIGN)); NetReceive(desc_p->dmamac_addr, length); -- cgit v1.2.3 From 1857075a7f00ff0a62b13170a78c70ff94e30f96 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Wed, 14 May 2014 19:30:29 +0100 Subject: net/designware: reorder struct dw_eth_dev to pack more efficiently. On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote: > The {r,t}xbuffs fields also need to be aligned. Previously this was done > implicitly because they immediately followed the descriptor tables. Make this > explicit and also move to the head of the struct. Looks like I managed to not actually commit the move of the field to the head of the struct! v3.1 follows.... Ian. 8<------------ >From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 1 May 2014 19:45:15 +0100 Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more efficiently. The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could be 256 or even larger. That means there is a potentially huge hole in the struct before those fields, so move them to the front where they are better packed. Moving them to the front also helps ensure that so long as dw_eth_dev is properly aligned (which it is since "net/designware: ensure device private data is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids having to worry too much about compiler specifics. The {r,t}xbuffs fields also need to be aligned. Previously this was done implicitly because they immediately followed the descriptor tables. Make this explicit and also move to the head of the struct. Signed-off-by: Ian Campbell Cc: Alexey Brodkin Tested-by: Siarhei Siamashka Reviewed-by: Siarhei Siamashka --- drivers/net/designware.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 382b0c7f0a..de2fdcb1f2 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -215,15 +215,14 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 interface; - u32 tx_currdescnum; - u32 rx_currdescnum; - struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); - char txbuffs[TX_TOTAL_BUFSIZE]; - char rxbuffs[RX_TOTAL_BUFSIZE]; + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; -- cgit v1.2.3 From 49692c5f517d8e44ed9db0de778728fe7d2a300c Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 8 May 2014 22:26:35 +0100 Subject: net/designware: Make DMA burst length configurable and reduce by default The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell Cc: Alexey Brodkin --- drivers/net/designware.c | 2 +- drivers/net/designware.h | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fa816bf2f6..7186e3b491 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -249,7 +249,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index de2fdcb1f2..ce51102052 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -77,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) -- cgit v1.2.3