From b32e11a7158063c6cd773087a2b3b5736da0a273 Mon Sep 17 00:00:00 2001 From: Nitin Jain Date: Fri, 16 Feb 2018 17:29:54 +0530 Subject: fpga: zynqmp: Add support to get the PCAP status for fpga info command This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command. Signed-off-by: Nitin Jain Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 57a4e6c88e..80388ae7f2 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -224,6 +224,20 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return ret; } +static int zynqmp_pcap_info(xilinx_desc *desc) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); + if (!ret) + printf("PCAP status\t0x%x\n", ret_payload[1]); + + return ret; +} + struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, + .info = zynqmp_pcap_info, }; -- cgit v1.2.3 From 19ed4b697b9732e0a5097bd233fba7e24dfe9146 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 1 Mar 2018 17:44:47 +0530 Subject: fpga: zynqmp: Update zynqmp_load() as per latest xilfpga Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Joe Hershberger --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ drivers/fpga/zynqmppl.c | 6 +----- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers/fpga') diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad3dc9aba5..3daf0e81d8 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -14,6 +14,8 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_NS 5 + enum { IDCODE, VERSION, diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 80388ae7f2..aae0efc734 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -209,13 +209,9 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); - if (bsize % 4) - bsize = bsize / 4 + 1; - else - bsize = bsize / 4; - buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); + bstype |= BIT(ZYNQMP_FPGA_BIT_NS); ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, bstype, ret_payload); if (ret) -- cgit v1.2.3 From 31bcb3444cbd5002ca9d8f6a3a2644092748cdba Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 15 Mar 2018 00:17:24 +0530 Subject: fpga: zynqmp: Fix the nonsecure bitstream loading issue Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Nava kishore Manne Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index aae0efc734..43e8b2520e 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include #include #include +#include #define DUMMY_WORD 0xffffffff @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize; debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); bstype |= BIT(ZYNQMP_FPGA_BIT_NS); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); -- cgit v1.2.3 From 71723aaec5e6dbfbc401d65461fe1cae98912e79 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 6 Mar 2018 17:37:09 +0530 Subject: fpga: zynq: Add delay after PCFG_PROG_B change There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 2ff716c252..db9bd12992 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -17,6 +17,7 @@ #include #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Setting PCFG_PROG_B signal to high */ control = readl(&devcfg_base->ctrl); writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Setting PCFG_PROG_B signal to low */ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { -- cgit v1.2.3