From 9ef9fe3455557161d076a821f0a65ee490198931 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Tue, 5 Dec 2017 15:58:00 +0800 Subject: ARM: socfpga: Rename the gen5 sdram driver to more specific name Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram.c | 536 ---------------------------------------- drivers/ddr/altera/sdram_gen5.c | 536 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 537 insertions(+), 537 deletions(-) delete mode 100644 drivers/ddr/altera/sdram.c create mode 100644 drivers/ddr/altera/sdram_gen5.c (limited to 'drivers/ddr') diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index d42fd4451d..ec1cb0b6e4 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,5 +7,5 @@ # Copyright (C) 2014 Altera Corporation ifdef CONFIG_ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o endif diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c deleted file mode 100644 index 821060459c..0000000000 --- a/drivers/ddr/altera/sdram.c +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright Altera Corporation (C) 2014-2015 - */ -#include -#include -#include -#include -#include -#include -#include -#include - -struct sdram_prot_rule { - u32 sdram_start; /* SDRAM start address */ - u32 sdram_end; /* SDRAM end address */ - u32 rule; /* SDRAM protection rule number: 0-19 */ - int valid; /* Rule valid or not? 1 - valid, 0 not*/ - - u32 security; - u32 portmask; - u32 result; - u32 lo_prot_id; - u32 hi_prot_id; -}; - -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; - -/** - * get_errata_rows() - Up the number of DRAM rows to cover entire address space - * @cfg: SDRAM controller configuration data - * - * SDRAM Failure happens when accessing non-existent memory. Artificially - * increase the number of rows so that the memory controller thinks it has - * 4GB of RAM. This function returns such amount of rows. - */ -static int get_errata_rows(const struct socfpga_sdram_config *cfg) -{ - /* Define constant for 4G memory - used for SDRAM errata workaround */ -#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) - const unsigned long long memsize = MEMSIZE_4G; - const unsigned int cs = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - const unsigned int rows = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - const unsigned int banks = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; - const unsigned int cols = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; - const unsigned int width = 8; - - unsigned long long newrows; - int bits, inewrowslog2; - - debug("workaround rows - memsize %lld\n", memsize); - debug("workaround rows - cs %d\n", cs); - debug("workaround rows - width %d\n", width); - debug("workaround rows - rows %d\n", rows); - debug("workaround rows - banks %d\n", banks); - debug("workaround rows - cols %d\n", cols); - - newrows = lldiv(memsize, cs * (width / 8)); - debug("rows workaround - term1 %lld\n", newrows); - - newrows = lldiv(newrows, (1 << banks) * (1 << cols)); - debug("rows workaround - term2 %lld\n", newrows); - - /* - * Compute the hamming weight - same as number of bits set. - * Need to see if result is ordinal power of 2 before - * attempting log2 of result. - */ - bits = generic_hweight32(newrows); - - debug("rows workaround - bits %d\n", bits); - - if (bits != 1) { - printf("SDRAM workaround failed, bits set %d\n", bits); - return rows; - } - - if (newrows > UINT_MAX) { - printf("SDRAM workaround rangecheck failed, %lld\n", newrows); - return rows; - } - - inewrowslog2 = __ilog2(newrows); - - debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); - - if (inewrowslog2 == -1) { - printf("SDRAM workaround failed, newrows %lld\n", newrows); - return rows; - } - - return inewrowslog2; -} - -/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) -{ - u32 lo_addr_bits; - u32 hi_addr_bits; - int ruleno = prule->rule; - - /* Select the rule */ - writel(ruleno, &sdr_ctrl->prot_rule_rdwr); - - /* Obtain the address bits */ - lo_addr_bits = prule->sdram_start >> 20ULL; - hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; - - debug("sdram set rule start %x, %d\n", lo_addr_bits, - prule->sdram_start); - debug("sdram set rule end %x, %d\n", hi_addr_bits, - prule->sdram_end); - - /* Set rule addresses */ - writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); - - /* Set rule protection ids */ - writel(prule->lo_prot_id | (prule->hi_prot_id << 12), - &sdr_ctrl->prot_rule_id); - - /* Set the rule data */ - writel(prule->security | (prule->valid << 2) | - (prule->portmask << 3) | (prule->result << 13), - &sdr_ctrl->prot_rule_data); - - /* write the rule */ - writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); - - /* Set rule number to 0 by default */ - writel(0, &sdr_ctrl->prot_rule_rdwr); -} - -static void sdram_get_rule(struct sdram_prot_rule *prule) -{ - u32 addr; - u32 id; - u32 data; - int ruleno = prule->rule; - - /* Read the rule */ - writel(ruleno, &sdr_ctrl->prot_rule_rdwr); - writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); - - /* Get the addresses */ - addr = readl(&sdr_ctrl->prot_rule_addr); - prule->sdram_start = (addr & 0xFFF) << 20; - prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; - - /* Get the configured protection IDs */ - id = readl(&sdr_ctrl->prot_rule_id); - prule->lo_prot_id = id & 0xFFF; - prule->hi_prot_id = (id >> 12) & 0xFFF; - - /* Get protection data */ - data = readl(&sdr_ctrl->prot_rule_data); - - prule->security = data & 0x3; - prule->valid = (data >> 2) & 0x1; - prule->portmask = (data >> 3) & 0x3FF; - prule->result = (data >> 13) & 0x1; -} - -static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) -{ - struct sdram_prot_rule rule; - int rules; - - /* Start with accepting all SDRAM transaction */ - writel(0x0, &sdr_ctrl->protport_default); - - /* Clear all protection rules for warm boot case */ - memset(&rule, 0, sizeof(rule)); - - for (rules = 0; rules < 20; rules++) { - rule.rule = rules; - sdram_set_rule(&rule); - } - - /* new rule: accept SDRAM */ - rule.sdram_start = sdram_start; - rule.sdram_end = sdram_end; - rule.lo_prot_id = 0x0; - rule.hi_prot_id = 0xFFF; - rule.portmask = 0x3FF; - rule.security = 0x3; - rule.result = 0; - rule.valid = 1; - rule.rule = 0; - - /* set new rule */ - sdram_set_rule(&rule); - - /* default rule: reject everything */ - writel(0x3ff, &sdr_ctrl->protport_default); -} - -static void sdram_dump_protection_config(void) -{ - struct sdram_prot_rule rule; - int rules; - - debug("SDRAM Prot rule, default %x\n", - readl(&sdr_ctrl->protport_default)); - - for (rules = 0; rules < 20; rules++) { - rule.rule = rules; - sdram_get_rule(&rule); - debug("Rule %d, rules ...\n", rules); - debug(" sdram start %x\n", rule.sdram_start); - debug(" sdram end %x\n", rule.sdram_end); - debug(" low prot id %d, hi prot id %d\n", - rule.lo_prot_id, - rule.hi_prot_id); - debug(" portmask %x\n", rule.portmask); - debug(" security %d\n", rule.security); - debug(" result %d\n", rule.result); - debug(" valid %d\n", rule.valid); - } -} - -/** - * sdram_write_verify() - write to register and verify the write. - * @addr: Register address - * @val: Value to be written and verified - * - * This function writes to a register, reads back the value and compares - * the result with the written value to check if the data match. - */ -static unsigned sdram_write_verify(const u32 *addr, const u32 val) -{ - u32 rval; - - debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); - writel(val, addr); - - debug(" Read and verify..."); - rval = readl(addr); - if (rval != val) { - debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", - addr, val, rval); - return -EINVAL; - } - - debug("correct!\n"); - return 0; -} - -/** - * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register - * @cfg: SDRAM controller configuration data - * - * Return the value of DRAM CTRLCFG register. - */ -static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) -{ - const u32 csbits = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - u32 addrorder = - (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> - SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; - - u32 ctrl_cfg = cfg->ctrl_cfg; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Set the addrorder field of the SDRAM control register - * based on the CSBITs setting. - */ - if (csbits == 1) { - if (addrorder != 0) - debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); - addrorder = 0; - } else if (csbits == 2) { - if (addrorder != 2) - debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); - addrorder = 2; - } - - ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; - ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; - - return ctrl_cfg; -} - -/** - * sdr_get_addr_rw() - Get the value of DRAM ADDRW register - * @cfg: SDRAM controller configuration data - * - * Return the value of DRAM ADDRW register. - */ -static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) -{ - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to - * log2(number of chip select bits). Since there's only - * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, - * which is the same as "chip selects" - 1. - */ - const int rows = get_errata_rows(cfg); - u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK; - - return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); -} - -/** - * sdr_load_regs() - Load SDRAM controller registers - * @cfg: SDRAM controller configuration data - * - * This function loads the register values into the SDRAM controller block. - */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) -{ - const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); - const u32 dram_addrw = sdr_get_addr_rw(cfg); - - debug("\nConfiguring CTRLCFG\n"); - writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); - - debug("Configuring DRAMTIMING1\n"); - writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); - - debug("Configuring DRAMTIMING2\n"); - writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); - - debug("Configuring DRAMTIMING3\n"); - writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); - - debug("Configuring DRAMTIMING4\n"); - writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); - - debug("Configuring LOWPWRTIMING\n"); - writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); - - debug("Configuring DRAMADDRW\n"); - writel(dram_addrw, &sdr_ctrl->dram_addrw); - - debug("Configuring DRAMIFWIDTH\n"); - writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); - - debug("Configuring DRAMDEVWIDTH\n"); - writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); - - debug("Configuring LOWPWREQ\n"); - writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); - - debug("Configuring DRAMINTR\n"); - writel(cfg->dram_intr, &sdr_ctrl->dram_intr); - - debug("Configuring STATICCFG\n"); - writel(cfg->static_cfg, &sdr_ctrl->static_cfg); - - debug("Configuring CTRLWIDTH\n"); - writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); - - debug("Configuring PORTCFG\n"); - writel(cfg->port_cfg, &sdr_ctrl->port_cfg); - - debug("Configuring FIFOCFG\n"); - writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); - - debug("Configuring MPPRIORITY\n"); - writel(cfg->mp_priority, &sdr_ctrl->mp_priority); - - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); - writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); - writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); - writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); - - debug("Configuring MPPACING_MPPACING_0\n"); - writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); - writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); - writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); - writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); - - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); - writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); - writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); - - debug("Configuring PHYCTRL_PHYCTRL_0\n"); - writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); - - debug("Configuring CPORTWIDTH\n"); - writel(cfg->cport_width, &sdr_ctrl->cport_width); - - debug("Configuring CPORTWMAP\n"); - writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); - - debug("Configuring CPORTRMAP\n"); - writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); - - debug("Configuring RFIFOCMAP\n"); - writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); - - debug("Configuring WFIFOCMAP\n"); - writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); - - debug("Configuring CPORTRDWR\n"); - writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); - - debug("Configuring DRAMODT\n"); - writel(cfg->dram_odt, &sdr_ctrl->dram_odt); - - debug("Configuring EXTRATIME1\n"); - writel(cfg->extratime1, &sdr_ctrl->extratime1); -} - -/** - * sdram_mmr_init_full() - Function to initialize SDRAM MMR - * @sdr_phy_reg: Value of the PHY control register 0 - * - * Initialize the SDRAM MMR. - */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) -{ - const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); - const unsigned int rows = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - int ret; - - writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - - sdr_load_regs(cfg); - - /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); - - /* only enable if the FPGA is programmed */ - if (fpgamgr_test_fpga_ready()) { - ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, - cfg->fpgaport_rst); - if (ret) - return ret; - } - - /* Restore the SDR PHY Register if valid */ - if (sdr_phy_reg != 0xffffffff) - writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); - - /* Final step - apply configuration changes */ - debug("Configuring STATICCFG\n"); - clrsetbits_le32(&sdr_ctrl->static_cfg, - SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, - 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - - sdram_set_protection_config(0, sdram_calculate_size() - 1); - - sdram_dump_protection_config(); - - return 0; -} - -/** - * sdram_calculate_size() - Calculate SDRAM size - * - * Calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. - */ -unsigned long sdram_calculate_size(void) -{ - unsigned long temp; - unsigned long row, bank, col, cs, width; - const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); - const unsigned int csbits = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - const unsigned int rowbits = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - - temp = readl(&sdr_ctrl->dram_addrw); - col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Use ROWBITS from Quartus/QSys to calculate SDRAM size - * since the FB specifies we modify ROWBITs to work around SDRAM - * controller issue. - */ - row = readl(&sysmgr_regs->iswgrp_handoff[4]); - if (row == 0) - row = rowbits; - /* - * If the stored handoff value for rows is greater than - * the field width in the sdr.dramaddrw register then - * something is very wrong. Revert to using the the #define - * value handed off by the SOCEDS tool chain instead of - * using a broken value. - */ - if (row > 31) - row = rowbits; - - bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Use CSBITs from Quartus/QSys to calculate SDRAM size - * since the FB specifies we modify CSBITs to work around SDRAM - * controller issue. - */ - cs = csbits; - - width = readl(&sdr_ctrl->dram_if_width); - - /* ECC would not be calculated as its not addressible */ - if (width == SDRAM_WIDTH_32BIT_WITH_ECC) - width = 32; - if (width == SDRAM_WIDTH_16BIT_WITH_ECC) - width = 16; - - /* calculate the SDRAM size base on this info */ - temp = 1 << (row + bank + col); - temp = temp * cs * (width / 8); - - debug("%s returns %ld\n", __func__, temp); - - return temp; -} diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c new file mode 100644 index 0000000000..821060459c --- /dev/null +++ b/drivers/ddr/altera/sdram_gen5.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Altera Corporation (C) 2014-2015 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct sdram_prot_rule { + u32 sdram_start; /* SDRAM start address */ + u32 sdram_end; /* SDRAM end address */ + u32 rule; /* SDRAM protection rule number: 0-19 */ + int valid; /* Rule valid or not? 1 - valid, 0 not*/ + + u32 security; + u32 portmask; + u32 result; + u32 lo_prot_id; + u32 hi_prot_id; +}; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_sdr_ctrl *sdr_ctrl = + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +/** + * get_errata_rows() - Up the number of DRAM rows to cover entire address space + * @cfg: SDRAM controller configuration data + * + * SDRAM Failure happens when accessing non-existent memory. Artificially + * increase the number of rows so that the memory controller thinks it has + * 4GB of RAM. This function returns such amount of rows. + */ +static int get_errata_rows(const struct socfpga_sdram_config *cfg) +{ + /* Define constant for 4G memory - used for SDRAM errata workaround */ +#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) + const unsigned long long memsize = MEMSIZE_4G; + const unsigned int cs = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + const unsigned int banks = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + const unsigned int cols = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; + const unsigned int width = 8; + + unsigned long long newrows; + int bits, inewrowslog2; + + debug("workaround rows - memsize %lld\n", memsize); + debug("workaround rows - cs %d\n", cs); + debug("workaround rows - width %d\n", width); + debug("workaround rows - rows %d\n", rows); + debug("workaround rows - banks %d\n", banks); + debug("workaround rows - cols %d\n", cols); + + newrows = lldiv(memsize, cs * (width / 8)); + debug("rows workaround - term1 %lld\n", newrows); + + newrows = lldiv(newrows, (1 << banks) * (1 << cols)); + debug("rows workaround - term2 %lld\n", newrows); + + /* + * Compute the hamming weight - same as number of bits set. + * Need to see if result is ordinal power of 2 before + * attempting log2 of result. + */ + bits = generic_hweight32(newrows); + + debug("rows workaround - bits %d\n", bits); + + if (bits != 1) { + printf("SDRAM workaround failed, bits set %d\n", bits); + return rows; + } + + if (newrows > UINT_MAX) { + printf("SDRAM workaround rangecheck failed, %lld\n", newrows); + return rows; + } + + inewrowslog2 = __ilog2(newrows); + + debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); + + if (inewrowslog2 == -1) { + printf("SDRAM workaround failed, newrows %lld\n", newrows); + return rows; + } + + return inewrowslog2; +} + +/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ +static void sdram_set_rule(struct sdram_prot_rule *prule) +{ + u32 lo_addr_bits; + u32 hi_addr_bits; + int ruleno = prule->rule; + + /* Select the rule */ + writel(ruleno, &sdr_ctrl->prot_rule_rdwr); + + /* Obtain the address bits */ + lo_addr_bits = prule->sdram_start >> 20ULL; + hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; + + debug("sdram set rule start %x, %d\n", lo_addr_bits, + prule->sdram_start); + debug("sdram set rule end %x, %d\n", hi_addr_bits, + prule->sdram_end); + + /* Set rule addresses */ + writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); + + /* Set rule protection ids */ + writel(prule->lo_prot_id | (prule->hi_prot_id << 12), + &sdr_ctrl->prot_rule_id); + + /* Set the rule data */ + writel(prule->security | (prule->valid << 2) | + (prule->portmask << 3) | (prule->result << 13), + &sdr_ctrl->prot_rule_data); + + /* write the rule */ + writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); + + /* Set rule number to 0 by default */ + writel(0, &sdr_ctrl->prot_rule_rdwr); +} + +static void sdram_get_rule(struct sdram_prot_rule *prule) +{ + u32 addr; + u32 id; + u32 data; + int ruleno = prule->rule; + + /* Read the rule */ + writel(ruleno, &sdr_ctrl->prot_rule_rdwr); + writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); + + /* Get the addresses */ + addr = readl(&sdr_ctrl->prot_rule_addr); + prule->sdram_start = (addr & 0xFFF) << 20; + prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; + + /* Get the configured protection IDs */ + id = readl(&sdr_ctrl->prot_rule_id); + prule->lo_prot_id = id & 0xFFF; + prule->hi_prot_id = (id >> 12) & 0xFFF; + + /* Get protection data */ + data = readl(&sdr_ctrl->prot_rule_data); + + prule->security = data & 0x3; + prule->valid = (data >> 2) & 0x1; + prule->portmask = (data >> 3) & 0x3FF; + prule->result = (data >> 13) & 0x1; +} + +static void +sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +{ + struct sdram_prot_rule rule; + int rules; + + /* Start with accepting all SDRAM transaction */ + writel(0x0, &sdr_ctrl->protport_default); + + /* Clear all protection rules for warm boot case */ + memset(&rule, 0, sizeof(rule)); + + for (rules = 0; rules < 20; rules++) { + rule.rule = rules; + sdram_set_rule(&rule); + } + + /* new rule: accept SDRAM */ + rule.sdram_start = sdram_start; + rule.sdram_end = sdram_end; + rule.lo_prot_id = 0x0; + rule.hi_prot_id = 0xFFF; + rule.portmask = 0x3FF; + rule.security = 0x3; + rule.result = 0; + rule.valid = 1; + rule.rule = 0; + + /* set new rule */ + sdram_set_rule(&rule); + + /* default rule: reject everything */ + writel(0x3ff, &sdr_ctrl->protport_default); +} + +static void sdram_dump_protection_config(void) +{ + struct sdram_prot_rule rule; + int rules; + + debug("SDRAM Prot rule, default %x\n", + readl(&sdr_ctrl->protport_default)); + + for (rules = 0; rules < 20; rules++) { + rule.rule = rules; + sdram_get_rule(&rule); + debug("Rule %d, rules ...\n", rules); + debug(" sdram start %x\n", rule.sdram_start); + debug(" sdram end %x\n", rule.sdram_end); + debug(" low prot id %d, hi prot id %d\n", + rule.lo_prot_id, + rule.hi_prot_id); + debug(" portmask %x\n", rule.portmask); + debug(" security %d\n", rule.security); + debug(" result %d\n", rule.result); + debug(" valid %d\n", rule.valid); + } +} + +/** + * sdram_write_verify() - write to register and verify the write. + * @addr: Register address + * @val: Value to be written and verified + * + * This function writes to a register, reads back the value and compares + * the result with the written value to check if the data match. + */ +static unsigned sdram_write_verify(const u32 *addr, const u32 val) +{ + u32 rval; + + debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); + writel(val, addr); + + debug(" Read and verify..."); + rval = readl(addr); + if (rval != val) { + debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", + addr, val, rval); + return -EINVAL; + } + + debug("correct!\n"); + return 0; +} + +/** + * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM CTRLCFG register. + */ +static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) +{ + const u32 csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + u32 addrorder = + (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; + + u32 ctrl_cfg = cfg->ctrl_cfg; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Set the addrorder field of the SDRAM control register + * based on the CSBITs setting. + */ + if (csbits == 1) { + if (addrorder != 0) + debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); + addrorder = 0; + } else if (csbits == 2) { + if (addrorder != 2) + debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); + addrorder = 2; + } + + ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; + ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; + + return ctrl_cfg; +} + +/** + * sdr_get_addr_rw() - Get the value of DRAM ADDRW register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM ADDRW register. + */ +static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) +{ + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to + * log2(number of chip select bits). Since there's only + * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, + * which is the same as "chip selects" - 1. + */ + const int rows = get_errata_rows(cfg); + u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK; + + return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); +} + +/** + * sdr_load_regs() - Load SDRAM controller registers + * @cfg: SDRAM controller configuration data + * + * This function loads the register values into the SDRAM controller block. + */ +static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +{ + const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); + const u32 dram_addrw = sdr_get_addr_rw(cfg); + + debug("\nConfiguring CTRLCFG\n"); + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); + + debug("Configuring DRAMTIMING1\n"); + writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); + + debug("Configuring DRAMTIMING2\n"); + writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); + + debug("Configuring DRAMTIMING3\n"); + writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); + + debug("Configuring DRAMTIMING4\n"); + writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); + + debug("Configuring LOWPWRTIMING\n"); + writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); + + debug("Configuring DRAMADDRW\n"); + writel(dram_addrw, &sdr_ctrl->dram_addrw); + + debug("Configuring DRAMIFWIDTH\n"); + writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); + + debug("Configuring DRAMDEVWIDTH\n"); + writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); + + debug("Configuring LOWPWREQ\n"); + writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); + + debug("Configuring DRAMINTR\n"); + writel(cfg->dram_intr, &sdr_ctrl->dram_intr); + + debug("Configuring STATICCFG\n"); + writel(cfg->static_cfg, &sdr_ctrl->static_cfg); + + debug("Configuring CTRLWIDTH\n"); + writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); + + debug("Configuring PORTCFG\n"); + writel(cfg->port_cfg, &sdr_ctrl->port_cfg); + + debug("Configuring FIFOCFG\n"); + writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); + + debug("Configuring MPPRIORITY\n"); + writel(cfg->mp_priority, &sdr_ctrl->mp_priority); + + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); + writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); + writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); + writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); + + debug("Configuring MPPACING_MPPACING_0\n"); + writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); + writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); + writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); + writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); + + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); + + debug("Configuring PHYCTRL_PHYCTRL_0\n"); + writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); + + debug("Configuring CPORTWIDTH\n"); + writel(cfg->cport_width, &sdr_ctrl->cport_width); + + debug("Configuring CPORTWMAP\n"); + writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); + + debug("Configuring CPORTRMAP\n"); + writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); + + debug("Configuring RFIFOCMAP\n"); + writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); + + debug("Configuring WFIFOCMAP\n"); + writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); + + debug("Configuring CPORTRDWR\n"); + writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); + + debug("Configuring DRAMODT\n"); + writel(cfg->dram_odt, &sdr_ctrl->dram_odt); + + debug("Configuring EXTRATIME1\n"); + writel(cfg->extratime1, &sdr_ctrl->extratime1); +} + +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * @sdr_phy_reg: Value of the PHY control register 0 + * + * Initialize the SDRAM MMR. + */ +int sdram_mmr_init_full(unsigned int sdr_phy_reg) +{ + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + int ret; + + writel(rows, &sysmgr_regs->iswgrp_handoff[4]); + + sdr_load_regs(cfg); + + /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ + writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); + + /* only enable if the FPGA is programmed */ + if (fpgamgr_test_fpga_ready()) { + ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, + cfg->fpgaport_rst); + if (ret) + return ret; + } + + /* Restore the SDR PHY Register if valid */ + if (sdr_phy_reg != 0xffffffff) + writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); + + /* Final step - apply configuration changes */ + debug("Configuring STATICCFG\n"); + clrsetbits_le32(&sdr_ctrl->static_cfg, + SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, + 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); + + sdram_set_protection_config(0, sdram_calculate_size() - 1); + + sdram_dump_protection_config(); + + return 0; +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +unsigned long sdram_calculate_size(void) +{ + unsigned long temp; + unsigned long row, bank, col, cs, width; + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const unsigned int csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rowbits = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + + temp = readl(&sdr_ctrl->dram_addrw); + col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Use ROWBITS from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify ROWBITs to work around SDRAM + * controller issue. + */ + row = readl(&sysmgr_regs->iswgrp_handoff[4]); + if (row == 0) + row = rowbits; + /* + * If the stored handoff value for rows is greater than + * the field width in the sdr.dramaddrw register then + * something is very wrong. Revert to using the the #define + * value handed off by the SOCEDS tool chain instead of + * using a broken value. + */ + if (row > 31) + row = rowbits; + + bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Use CSBITs from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify CSBITs to work around SDRAM + * controller issue. + */ + cs = csbits; + + width = readl(&sdr_ctrl->dram_if_width); + + /* ECC would not be calculated as its not addressible */ + if (width == SDRAM_WIDTH_32BIT_WITH_ECC) + width = 32; + if (width == SDRAM_WIDTH_16BIT_WITH_ECC) + width = 16; + + /* calculate the SDRAM size base on this info */ + temp = 1 << (row + bank + col); + temp = temp * cs * (width / 8); + + debug("%s returns %ld\n", __func__, temp); + + return temp; +} -- cgit v1.2.3 From 5658a299bdd2f616277eaea5d601976108d18326 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Tue, 5 Dec 2017 15:58:02 +0800 Subject: ARM: socfpga: Add DDR driver for Arria 10 Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/sdram.h | 2 + arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_arria10.c | 741 +++++++++++++++++++++ 4 files changed, 746 insertions(+) create mode 100644 drivers/ddr/altera/sdram_arria10.c (limited to 'drivers/ddr') diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 1a4b22accd..79cb9e6064 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -9,6 +9,8 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include #endif #endif diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h index 8ae8d1bc96..25b82fb285 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h @@ -7,6 +7,7 @@ #define _SOCFPGA_SDRAM_ARRIA10_H_ #ifndef __ASSEMBLY__ +int ddr_calibration_sequence(void); struct socfpga_ecc_hmc { u32 ip_rev_id; @@ -203,6 +204,7 @@ struct socfpga_io48_mmr { u32 niosreserve1; u32 niosreserve2; }; + #endif /*__ASSEMBLY__*/ #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000 diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index ec1cb0b6e4..f05314a373 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -8,4 +8,5 @@ ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c new file mode 100644 index 0000000000..d953c376b8 --- /dev/null +++ b/drivers/ddr/altera/sdram_arria10.c @@ -0,0 +1,741 @@ +/* + * Copyright (C) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void sdram_mmr_init(void); +static u64 sdram_size_calc(void); + +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) + +#define ARRIA_DDR_CONFIG(A, B, C, R) \ + (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) +#define DDR_REG_SEQ2CORE 0xFFD0507C +#define DDR_REG_CORE2SEQ 0xFFD05078 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_SIZE_2GB_HEX 0x80000000 +#define DDR_MAX_TRIES 0x00100000 + +#define IO48_MMR_DRAMSTS 0xFFCFA0EC +#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 +#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 +#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 + +#define SEQ2CORE_MASK 0xF +#define CORE2SEQ_INT_REQ 0xF +#define SEQ2CORE_INT_RESP_BIT 3 + +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = + (void *)SOCFPGA_SDR_ADDRESS; +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; + +/* The following are the supported configurations */ +static u32 ddr_config[] = { + /* Chip - Row - Bank - Column Style */ + /* All Types */ + ARRIA_DDR_CONFIG(0, 3, 10, 12), + ARRIA_DDR_CONFIG(0, 3, 10, 13), + ARRIA_DDR_CONFIG(0, 3, 10, 14), + ARRIA_DDR_CONFIG(0, 3, 10, 15), + ARRIA_DDR_CONFIG(0, 3, 10, 16), + ARRIA_DDR_CONFIG(0, 3, 10, 17), + /* LPDDR x16 */ + ARRIA_DDR_CONFIG(0, 3, 11, 14), + ARRIA_DDR_CONFIG(0, 3, 11, 15), + ARRIA_DDR_CONFIG(0, 3, 11, 16), + ARRIA_DDR_CONFIG(0, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(0, 4, 10, 14), + ARRIA_DDR_CONFIG(0, 4, 10, 15), + ARRIA_DDR_CONFIG(0, 4, 10, 16), + ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ + /* Chip - Bank - Row - Column Style */ + ARRIA_DDR_CONFIG(1, 3, 10, 12), + ARRIA_DDR_CONFIG(1, 3, 10, 13), + ARRIA_DDR_CONFIG(1, 3, 10, 14), + ARRIA_DDR_CONFIG(1, 3, 10, 15), + ARRIA_DDR_CONFIG(1, 3, 10, 16), + ARRIA_DDR_CONFIG(1, 3, 10, 17), + ARRIA_DDR_CONFIG(1, 3, 11, 14), + ARRIA_DDR_CONFIG(1, 3, 11, 15), + ARRIA_DDR_CONFIG(1, 3, 11, 16), + ARRIA_DDR_CONFIG(1, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(1, 4, 10, 14), + ARRIA_DDR_CONFIG(1, 4, 10, 15), + ARRIA_DDR_CONFIG(1, 4, 10, 16), + ARRIA_DDR_CONFIG(1, 4, 10, 17), +}; + +static int match_ddr_conf(u32 ddr_conf) +{ + int i; + + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +/* Check whether SDRAM is successfully Calibrated */ +static int is_sdram_cal_success(void) +{ + return readl(&socfpga_ecc_hmc_base->ddrcalstat); +} + +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) +{ + u32 reg = readl(ereg); + + return (reg & BIT(bit)) ? 1 : 0; +} + +static unsigned char ddr_wait_bit(u32 ereg, u32 bit, + u32 expected, u32 timeout_usec) +{ + u32 tmr; + + for (tmr = 0; tmr < timeout_usec; tmr += 100) { + udelay(100); + WATCHDOG_RESET(); + if (ddr_get_bit(ereg, bit) == expected) + return 0; + } + + return 1; +} + +static int emif_clear(void) +{ + u32 i = DDR_MAX_TRIES; + u8 ret = 0; + + writel(0, DDR_REG_CORE2SEQ); + + do { + ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_MASK, 1, 50, 0); + } while (ret && (--i > 0)); + + return !i; +} + +static int emif_reset(void) +{ + u32 c2s, s2c; + + c2s = readl(DDR_REG_CORE2SEQ); + s2c = readl(DDR_REG_SEQ2CORE); + + debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2), + readl(IO48_MMR_DRAMSTS)); + + if ((s2c & SEQ2CORE_MASK) && emif_clear()) { + debug("failed emif_clear()\n"); + return -EPERM; + } + + writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); + + if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { + debug("emif_reset failed to see interrupt acknowledge\n"); + return -EPERM; + } else { + debug("emif_reset interrupt acknowledged\n"); + } + + if (emif_clear()) { + debug("emif_clear() failed\n"); + return -EPERM; + } + debug("emif_reset interrupt cleared\n"); + + debug("nr0=%08x nr1=%08x nr2=%08x\n", + readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2)); + + return 0; +} + +static int ddr_setup(void) +{ + int i, j, ddr_setup_complete = 0; + + /* Try 3 times to do a calibration */ + for (i = 0; (i < 3) && !ddr_setup_complete; i++) { + WATCHDOG_RESET(); + + /* A delay to wait for calibration bit to set */ + for (j = 0; (j < 10) && !ddr_setup_complete; j++) { + mdelay(500); + ddr_setup_complete = is_sdram_cal_success(); + } + + if (!ddr_setup_complete) + if (emif_reset()) + puts("Error: Failed to reset EMIF\n"); + } + + /* After 3 times trying calibration */ + if (!ddr_setup_complete) { + puts("Error: Could Not Calibrate SDRAM\n"); + return -EPERM; + } + + return 0; +} + +/* Function to startup the SDRAM*/ +static int sdram_startup(void) +{ + /* Release NOC ddr scheduler from reset */ + socfpga_reset_deassert_noc_ddr_scheduler(); + + /* Bringup the DDR (calibration and configuration) */ + return ddr_setup(); +} + +static u64 sdram_size_calc(void) +{ + u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); + + u64 size = BIT(((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) + + (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK)); + + size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & + ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); + + debug("SDRAM size=%llu", size); + + return size; +} + +/* Function to initialize SDRAM MMR and NOC DDR scheduler*/ +static void sdram_mmr_init(void) +{ + u32 update_value, io48_value; + u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); + u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); + u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); + u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); + u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); + u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); + u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); + u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); + u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); + u32 ddrioctl; + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (0x20 for 32bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { + update_value = readl(&socfpga_io48_mmr_base->niosreserve0); + writel(((update_value & 0xFF) >> 5), + &socfpga_ecc_hmc_base->ddrioctrl); + } + + ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); + + /* Set the DDR Configuration [0xFFD12400] */ + io48_value = ARRIA_DDR_CONFIG( + ((ctrlcfg1 & + IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >> + IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT), + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT), + (dramaddrw & + IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK), + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT)); + + update_value = match_ddr_conf(io48_value); + if (update_value) + writel(update_value, + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); + + /* + * Configure DDR timing [0xFFD1240C] + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + u32 ctrlcfg0_cfg_ctrl_burst_len = + (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >> + IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT; + + u32 caltim0_cfg_act_to_rdwr = caltim0 & + IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK; + + u32 caltim0_cfg_act_to_act = + (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >> + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT; + + u32 caltim0_cfg_act_to_act_db = + (caltim0 & + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >> + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT; + + u32 caltim1_cfg_rd_to_wr = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT; + + u32 caltim1_cfg_rd_to_rd_dc = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT; + + u32 caltim1_cfg_rd_to_wr_dc = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT; + + u32 caltim2_cfg_rd_to_pch = + (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >> + IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT; + + u32 caltim3_cfg_wr_to_rd = + (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >> + IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT; + + u32 caltim3_cfg_wr_to_rd_dc = + (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >> + IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT; + + u32 caltim4_cfg_pch_to_valid = + (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >> + IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT; + + u32 caltim9_cfg_4_act_to_act = caltim9 & + IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK; + + update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + + caltim0_cfg_act_to_rdwr - + (ctrlcfg0_cfg_ctrl_burst_len >> 2)); + + io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & + ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + + (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr + + caltim4_cfg_pch_to_valid); + + writel(((caltim0_cfg_act_to_act << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | + (update_value << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | + (io48_value << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | + ((ctrlcfg0_cfg_ctrl_burst_len >> 2) << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | + (caltim1_cfg_rd_to_wr << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | + (caltim3_cfg_wr_to_rd << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | + (((ddrioctl == 1) ? 1 : 0) << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), + &socfpga_noc_ddr_scheduler_base-> + ddr_t_main_scheduler_ddrtiming); + + /* Configure DDR mode [0xFFD12410] [precharge = 0] */ + writel(((ddrioctl ? 0 : 1) << + ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); + + /* Configure the read latency [0xFFD12414] */ + writel(((socfpga_io48_mmr_base->dramtiming0 & + ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + + DDR_READ_LATENCY_DELAY, + &socfpga_noc_ddr_scheduler_base-> + ddr_t_main_scheduler_readlatency); + + /* + * Configuring timing values concerning activate commands + * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] + */ + writel(((caltim0_cfg_act_to_act_db << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | + (caltim9_cfg_4_act_to_act << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | + (ARRIA10_SDR_ACTIVATE_FAWBANK << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); + + /* + * Configuring timing values concerning device to device data bus + * ownership change [0xFFD1243C] + */ + writel(((caltim1_cfg_rd_to_rd_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | + (caltim1_cfg_rd_to_wr_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | + (caltim3_cfg_wr_to_rd_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); + + /* Enable or disable the SDRAM ECC */ + if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) { + setbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); + } else { + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); + } +} + +struct firewall_entry { + const char *prop_name; + const u32 cfg_addr; + const u32 en_addr; + const u32 en_bit; +}; +#define FW_MPU_FPGA_ADDRESS \ + ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\ + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS) + +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \ + (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \ + offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR)) + +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \ + (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \ + offsetof(struct socfpga_noc_fw_ddr_l3, ADDR)) + +const struct firewall_entry firewall_table[] = { + { + "mpu0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK + }, + { + "mpu1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK + }, + { + "mpu2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK + }, + { + "mpu3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK + }, + { + "l3-0", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK + }, + { + "l3-1", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK + }, + { + "l3-2", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK + }, + { + "l3-3", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK + }, + { + "l3-4", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK + }, + { + "l3-5", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK + }, + { + "l3-6", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK + }, + { + "l3-7", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK + }, + { + "fpga2sdram0-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK + }, + { + "fpga2sdram0-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK + }, + { + "fpga2sdram0-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK + }, + { + "fpga2sdram0-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK + }, + { + "fpga2sdram1-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK + }, + { + "fpga2sdram1-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK + }, + { + "fpga2sdram1-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK + }, + { + "fpga2sdram1-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK + }, + { + "fpga2sdram2-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK + }, + { + "fpga2sdram2-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK + }, + { + "fpga2sdram2-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK + }, + { + "fpga2sdram2-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK + }, + +}; + +static int of_sdram_firewall_setup(const void *blob) +{ + int child, i, node, ret; + u32 start_end[2]; + char name[32]; + + node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC); + if (node < 0) + return -ENXIO; + + child = fdt_first_subnode(blob, node); + if (child < 0) + return -ENXIO; + + /* set to default state */ + writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); + writel(0, &socfpga_noc_fw_ddr_l3_base->enable); + + + for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { + sprintf(name, "%s", firewall_table[i].prop_name); + ret = fdtdec_get_int_array(blob, child, name, + start_end, 2); + if (ret) { + sprintf(name, "altr,%s", firewall_table[i].prop_name); + ret = fdtdec_get_int_array(blob, child, name, + start_end, 2); + if (ret) + continue; + } + + writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) | + (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB), + firewall_table[i].cfg_addr); + setbits_le32(firewall_table[i].en_addr, + firewall_table[i].en_bit); + } + + return 0; +} + +int ddr_calibration_sequence(void) +{ + WATCHDOG_RESET(); + + /* Check to see if SDRAM cal was success */ + if (sdram_startup()) { + puts("DDRCAL: Failed\n"); + return -EPERM; + } + + puts("DDRCAL: Success\n"); + + WATCHDOG_RESET(); + + /* initialize the MMR register */ + sdram_mmr_init(); + + /* assigning the SDRAM size */ + u64 size = sdram_size_calc(); + + /* + * If size is less than zero, this is invalid/weird value from + * calculation, use default Config size. + * Up to 2GB is supported, 2GB would be used if more than that. + */ + if (size <= 0) + gd->ram_size = PHYS_SDRAM_1_SIZE; + else if (DDR_SIZE_2GB_HEX <= size) + gd->ram_size = DDR_SIZE_2GB_HEX; + else + gd->ram_size = (u32)size; + + /* setup the dram info within bd */ + dram_init_banksize(); + + if (of_sdram_firewall_setup(gd->fdt_blob)) + puts("FW: Error Configuring Firewall\n"); + + return 0; +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> 20; + i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i++) { +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + set_section_dcache(i, DCACHE_WRITETHROUGH); +#else + set_section_dcache(i, DCACHE_WRITEBACK); +#endif + } + + /* same as above but just that we would want cacheable for ocram too */ + i = CONFIG_SYS_INIT_RAM_ADDR >> 20; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + set_section_dcache(i, DCACHE_WRITETHROUGH); +#else + set_section_dcache(i, DCACHE_WRITEBACK); +#endif +} -- cgit v1.2.3 From 901af3e903c09c7681197a03367d82286f9f6e3f Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Tue, 5 Dec 2017 15:58:03 +0800 Subject: configs: Add DDR Kconfig support for Arria 10 This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee Reviewed-by: Dinh Nguyen --- arch/arm/mach-socfpga/Kconfig | 1 + drivers/ddr/altera/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/ddr') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 824c9fc2ba..b8fc81b20c 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -10,6 +10,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool select SPL_BOARD_INIT if SPL + select ALTERA_SDRAM config TARGET_SOCFPGA_CYCLONE5 bool diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 021ec1d857..2b28a97f6e 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,5 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" - depends on TARGET_SOCFPGA_GEN5 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 help Enable DDR SDRAM controller for the SoCFPGA devices. -- cgit v1.2.3