From 78475d2572615471d3c047e61481a68859d0dd7f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 23 Jul 2022 13:05:12 -0400 Subject: Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_INTLV_256B Signed-off-by: Tom Rini --- drivers/ddr/fsl/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/ddr') diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index d93ed8d2fe..22400a9b8b 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING timing parameters are extracted from datasheet and hard-coded into header files or board specific files. +config SYS_FSL_DDR_INTLV_256B + bool "Enforce 256-byte interleave" + help + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape SoCs + with ARM core. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" -- cgit v1.2.3