From 2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 10 May 2018 13:28:29 +1200 Subject: ARM: mvebu: a38x: sync ddr training code with upstream This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr_topology_def.h | 83 +++++++++++++---------------- 1 file changed, 37 insertions(+), 46 deletions(-) (limited to 'drivers/ddr/marvell/a38x/ddr_topology_def.h') diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index aa98774e78..2c589eb3a6 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -9,38 +9,13 @@ #include "ddr3_training_ip_def.h" #include "ddr3_topology_def.h" -#if defined(CONFIG_ARMADA_38X) -#include "ddr3_a38x.h" +#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) +#include "mv_ddr_plat.h" #endif -/* bus width in bits */ -enum hws_bus_width { - BUS_WIDTH_4, - BUS_WIDTH_8, - BUS_WIDTH_16, - BUS_WIDTH_32 -}; - -enum hws_temperature { - HWS_TEMP_LOW, - HWS_TEMP_NORMAL, - HWS_TEMP_HIGH -}; - -enum hws_mem_size { - MEM_512M, - MEM_1G, - MEM_2G, - MEM_4G, - MEM_8G, - MEM_SIZE_LAST -}; - -enum hws_timing { - HWS_TIM_DEFAULT, - HWS_TIM_1T, - HWS_TIM_2T -}; +#include "mv_ddr_topology.h" +#include "mv_ddr_spd.h" +#include "ddr3_logging_def.h" struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ @@ -66,11 +41,11 @@ struct if_params { /* Speed Bin Table */ enum hws_speed_bin speed_bin_index; - /* bus width of memory */ - enum hws_bus_width bus_width; + /* sdram device width */ + enum mv_ddr_dev_width bus_width; - /* Bus memory size (MBit) */ - enum hws_mem_size memory_size; + /* total sdram capacity per die, megabits */ + enum mv_ddr_die_capacity memory_size; /* The DDR frequency for each interfaces */ enum hws_ddr_freq memory_freq; @@ -88,33 +63,49 @@ struct if_params { u8 cas_l; /* operation temperature */ - enum hws_temperature interface_temp; - - /* 2T vs 1T mode (by default computed from number of CSs) */ - enum hws_timing timing; + enum mv_ddr_temperature interface_temp; }; -struct hws_topology_map { +struct mv_ddr_topology_map { + /* debug level configuration */ + enum mv_ddr_debug_level debug_level; + /* Number of interfaces (default is 12) */ u8 if_act_mask; /* Controller configuration per interface */ struct if_params interface_params[MAX_INTERFACE_NUM]; - /* BUS per interface (default is 4) */ - u8 num_of_bus_per_interface; - /* Bit mask for active buses */ - u8 bus_act_mask; + u16 bus_act_mask; + + /* source of ddr configuration data */ + enum mv_ddr_cfg_src cfg_src; + + /* raw spd data */ + union mv_ddr_spd_data spd_data; + + /* timing parameters */ + unsigned int timing_data[MV_DDR_TDATA_LAST]; }; /* DDR3 training global configuration parameters */ struct tune_train_params { u32 ck_delay; - u32 ck_delay_16; - u32 p_finger; - u32 n_finger; u32 phy_reg3_val; + u32 g_zpri_data; + u32 g_znri_data; + u32 g_zpri_ctrl; + u32 g_znri_ctrl; + u32 g_zpodt_data; + u32 g_znodt_data; + u32 g_zpodt_ctrl; + u32 g_znodt_ctrl; + u32 g_dic; + u32 g_odt_config; + u32 g_rtt_nom; + u32 g_rtt_wr; + u32 g_rtt_park; }; #endif /* _DDR_TOPOLOGY_DEF_H */ -- cgit v1.2.3 From e6f61622d32327907f824154c7f88ddce3c700cc Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 10 May 2018 13:28:30 +1200 Subject: ARM: mvebu: a38x: restore support for setting timing This restores support for configuring the timing mode based on the ddr_topology. This was originally implemented in commit 90bcc3d38d2b ("driver/ddr: Add support for setting timing in hws_topology_map") but was removed as part of the upstream sync. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- board/CZ.NIC/turris_omnia/turris_omnia.c | 6 ++++-- board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 3 ++- board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 3 ++- board/gdsys/a38x/controlcenterdc.c | 3 ++- board/solidrun/clearfog/clearfog.c | 3 ++- drivers/ddr/marvell/a38x/ddr3_training.c | 8 ++++++++ drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++ drivers/ddr/marvell/a38x/mv_ddr_plat.c | 5 ----- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 6 ++++++ 9 files changed, 29 insertions(+), 11 deletions(-) (limited to 'drivers/ddr/marvell/a38x/ddr_topology_def.h') diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 29f81cdccf..da663cf1bb 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -214,7 +214,8 @@ static struct mv_ddr_topology_map board_topology_map_1g = { MV_DDR_DIE_CAP_4GBIT, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_NORMAL} }, /* temperature */ + MV_DDR_TEMP_NORMAL, /* temperature */ + MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ @@ -235,7 +236,8 @@ static struct mv_ddr_topology_map board_topology_map_2g = { MV_DDR_DIE_CAP_8GBIT, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_NORMAL} }, /* temperature */ + MV_DDR_TEMP_NORMAL, /* temperature */ + MV_DDR_TIM_2T} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index e39dc75f92..92d7ae77f0 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_DIE_CAP_2GBIT, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index ee12ca68ec..a8cfe8af0a 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_DIE_CAP_4GBIT, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index f750e47b72..320bc100c9 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -53,7 +53,8 @@ static struct mv_ddr_topology_map ddr_topology_map = { MV_DDR_DIE_CAP_4GBIT, /* mem_size */ DDR_FREQ_533, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index cc11feb85e..ede303d4eb 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -83,7 +83,8 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_DIE_CAP_4GBIT, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_wl cas_l */ - MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_DEFAULT} }, /* timing */ BUS_MASK_32BIT, /* Busses mask */ MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 1f26d506da..799c5ba089 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -365,6 +365,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); enum hws_ddr_freq freq = tm->interface_params[0].memory_freq; + enum mv_ddr_timing timing; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n", @@ -603,8 +604,12 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ DUNIT_CTRL_HIGH_REG, (init_cntr_prm->msys_init << 7), (1 << 7))); + timing = tm->interface_params[if_id].timing; + if (mode_2t != 0xff) { t2t = mode_2t; + } else if (timing != MV_DDR_TIM_DEFAULT) { + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* calculate number of CS (per interface) */ CHECK_STATUS(calc_cs_num @@ -1268,6 +1273,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); unsigned int tclk; + enum mv_ddr_timing timing = tm->interface_params[if_id].timing; DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("dev %d access %d IF %d freq %d\n", dev_num, @@ -1410,6 +1416,8 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, /* Calculate 2T mode */ if (mode_2t != 0xff) { t2t = mode_2t; + } else if (timing != MV_DDR_TIM_DEFAULT) { + t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0; } else { /* Calculate number of CS per interface */ CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index 2c589eb3a6..812224909a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -64,6 +64,9 @@ struct if_params { /* operation temperature */ enum mv_ddr_temperature interface_temp; + + /* 2T vs 1T mode (by default computed from number of CSs) */ + enum mv_ddr_timing timing; }; struct mv_ddr_topology_map { diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c index ce672e9dd4..2070bb38b0 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c @@ -674,11 +674,6 @@ static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) dfs_low_freq = DFS_LOW_FREQ_VALUE; calibration_update_control = 1; -#ifdef CONFIG_ARMADA_38X - /* For a38x only, change to 2T mode to resolve low freq instability */ - mode_2t = 1; -#endif - ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq); return MV_OK; diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h index eb017a1497..7bef2d1e0e 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h +++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h @@ -36,6 +36,12 @@ enum mv_ddr_temperature { MV_DDR_TEMP_HIGH }; +enum mv_ddr_timing { + MV_DDR_TIM_DEFAULT, + MV_DDR_TIM_1T, + MV_DDR_TIM_2T +}; + enum mv_ddr_timing_data { MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */ MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */ -- cgit v1.2.3