From 2b4ffbf6b4944a0b3125fd2c9c0ba3568264367a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 10 May 2018 13:28:29 +1200 Subject: ARM: mvebu: a38x: sync ddr training code with upstream This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_ip_def.h | 34 +++++++++++++++++++++---- 1 file changed, 29 insertions(+), 5 deletions(-) (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip_def.h') diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h index 2a30f80f79..2318ceba29 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h @@ -6,8 +6,6 @@ #ifndef _DDR3_TRAINING_IP_DEF_H #define _DDR3_TRAINING_IP_DEF_H -#include "silicon_if.h" - #define PATTERN_55 0x55555555 #define PATTERN_AA 0xaaaaaaaa #define PATTERN_80 0x80808080 @@ -35,6 +33,7 @@ #define ADLL_RX_LENGTH 32 #define PARAM_NOT_CARE 0 +#define PARAM_UNDEFINED 0xffffffff #define READ_LEVELING_PHY_OFFSET 2 #define WRITE_LEVELING_PHY_OFFSET 0 @@ -99,6 +98,8 @@ #define _1G 0x40000000 #define _2G 0x80000000 +#define _4G 0x100000000 +#define _8G 0x200000000 #define ADDR_SIZE_512MB 0x04000000 #define ADDR_SIZE_1GB 0x08000000 @@ -163,10 +164,33 @@ enum hws_wl_supp { ALIGN_SHIFT }; +enum mv_ddr_tip_bit_state { + BIT_LOW_UI, + BIT_HIGH_UI, + BIT_SPLIT_IN, + BIT_SPLIT_OUT, + BIT_STATE_LAST +}; + +enum mv_ddr_tip_byte_state{ + BYTE_NOT_DEFINED, + BYTE_HOMOGENEOUS_LOW = 0x1, + BYTE_HOMOGENEOUS_HIGH = 0x2, + BYTE_HOMOGENEOUS_SPLIT_IN = 0x4, + BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8, + BYTE_SPLIT_OUT_MIX = 0x10, + BYTE_STATE_LAST +}; + struct reg_data { - u32 reg_addr; - u32 reg_data; - u32 reg_mask; + unsigned int reg_addr; + unsigned int reg_data; + unsigned int reg_mask; +}; + +enum dm_direction { + DM_DIR_INVERSE, + DM_DIR_DIRECT }; #endif /* _DDR3_TRAINING_IP_DEF_H */ -- cgit v1.2.3