From 66869f955417b89dbf6b7cbb72738b2205a26bf8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 19 Mar 2015 09:30:26 -0700 Subject: drivers/ddr/fsl: Update DDR driver for DDR4 Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun --- drivers/ddr/fsl/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/ddr/fsl/main.c') diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b72b24290e..fa223834f2 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -453,7 +453,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, retval = compute_dimm_parameters( i, spd, pdimm, j); #ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { + if (!j && retval) { printf("SPD error on controller %d! " "Trying fallback to raw timing " "calculation\n", i); -- cgit v1.2.3