From 93a8ed868583460ab9f3796fdc92f4713bf759a9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 29 May 2018 18:04:15 +0200 Subject: ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- drivers/ddr/altera/sdram_arria10.c | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'drivers/ddr/altera/sdram_arria10.c') diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 706a038b88..1f2b7f4819 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -713,28 +713,3 @@ int ddr_calibration_sequence(void) return 0; } - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> 20; - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } - - /* same as above but just that we would want cacheable for ocram too */ - i = CONFIG_SYS_INIT_RAM_ADDR >> 20; -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif -} -- cgit v1.2.3 From 07252f6f7e37e23cb43245dcddf8ea8f1d45dec1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 May 2018 17:22:47 +0200 Subject: ddr: altera: Add ECC DRAM scrubbing support for Arria10 The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- drivers/ddr/altera/sdram_arria10.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'drivers/ddr/altera/sdram_arria10.c') diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 1f2b7f4819..29ea7492f3 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -215,6 +215,30 @@ static int ddr_setup(void) return 0; } +static int sdram_is_ecc_enabled(void) +{ + return !!(readl(&socfpga_ecc_hmc_base->eccctrl) & + ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK); +} + +/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits(u32 size) +{ + icache_enable(); + + memset(0, 0, 0x8000); + gd->arch.tlb_addr = 0x4000; + gd->arch.tlb_size = PGTABLE_SIZE; + + dcache_enable(); + + printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20); + memset((void *)0x8000, 0, size - 0x8000); + flush_dcache_all(); + printf("DDRCAL: Scrubbing ECC RAM done.\n"); + dcache_disable(); +} + /* Function to startup the SDRAM*/ static int sdram_startup(void) { @@ -711,5 +735,8 @@ int ddr_calibration_sequence(void) if (of_sdram_firewall_setup(gd->fdt_blob)) puts("FW: Error Configuring Firewall\n"); + if (sdram_is_ecc_enabled()) + sdram_init_ecc_bits(gd->ram_size); + return 0; } -- cgit v1.2.3