From 4707fb50cc9f815996be5f2e5a8660de852b2c37 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 13 Oct 2006 21:09:09 +0200 Subject: Preliminary patch adding support for the MarelV38B board. --- board/v38b/ethaddr.c | 254 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 254 insertions(+) create mode 100644 board/v38b/ethaddr.c (limited to 'board/v38b/ethaddr.c') diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c new file mode 100644 index 0000000000..105608051c --- /dev/null +++ b/board/v38b/ethaddr.c @@ -0,0 +1,254 @@ +/* + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define GPIO_ENABLE (MPC5XXX_WU_GPIO) + +/* Open Drain Emulation Register */ +#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) + +/* Data Direction Register */ +#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) + +/* Data Value Out Register */ +#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) + +/* Interrupt Enable Register */ +#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) + +/* Individual Interrupt Enable Register */ +#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) + +/* Interrupt Type Register */ +#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) + +/* Master Enable Register */ +#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) + +/* Data Input Value Register */ +#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) + +/* Status Register */ +#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) + +#define PSC6_0 0x10000000 +#define WKUP_7 0x80000000 + +/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ +#define GPIO_PIN PSC6_0 + +#define NO_ERROR 0 +#define ERR_NO_NUMBER 1 +#define ERR_BAD_NUMBER 2 + +typedef volatile unsigned long GPIO_REG; +typedef GPIO_REG *GPIO_REG_PTR; + +static int is_high(void); +static int check_device(void); +static void io_out(int value); +static void io_input(void); +static void io_output(void); +static void init_gpio(void); +static void read_byte(unsigned char *data); +static void write_byte(unsigned char command); + +void read_2501_memory(unsigned char *psernum, unsigned char *perr); +void board_get_enetaddr(uchar *enetaddr); + +static int is_high() +{ + return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); +} + +static void io_out(int value) +{ + if (value) + *((vu_long *) GPIO_DVOR) |= GPIO_PIN; + else + *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; +} + +static void io_input() +{ + *((vu_long *) GPIO_DDR) &= ~GPIO_PIN; + udelay(3); /* allow input to settle */ +} + +static void io_output() +{ + *((vu_long *) GPIO_DDR) |= GPIO_PIN; +} + +static void init_gpio() +{ + *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ +} + +void read_2501_memory(unsigned char *psernum, unsigned char *perr) +{ +#define NBYTES 28 + unsigned char crcval, i; + unsigned char buf[NBYTES]; + + *perr = 0; + crcval = 0; + + for (i=0; i> 1; + } +} + +static void read_byte(unsigned char *data) +{ + unsigned char i, rdat = 0; + + for (i=0; i<8; i++) { + /* read one bit from one-wire device */ + + /* 1 - 15 us low starts bit slot */ + io_out(0); + io_output(); + udelay(0); + + /* allow line to be pulled high */ + io_input(); + + /* delay 10 us */ + udelay(10); + + /* now sample input status */ + if (is_high()) + rdat = (rdat >> 1) | 0x80; + else + rdat = rdat >> 1; + + udelay(60); /* at least 60 us */ + } + /* copy the return value */ + *data = rdat; +} + +void board_get_enetaddr(uchar *enetaddr) +{ + unsigned char sn[6], err=NO_ERROR; + + init_gpio(); + + read_2501_memory(sn, &err); + + if (err == NO_ERROR) { + sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", + sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); + printf("MAC address: %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } + else { + sprintf(enetaddr, "00:01:02:03:04:05"); + printf("Error reading MAC address.\n"); + printf("Setting default to %s\n", enetaddr); + setenv("ethaddr", enetaddr); + } +} -- cgit v1.2.3 From fcfed4f2f234836a0b308fd0a782f4625cd40bad Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 18 Oct 2006 22:44:38 +0200 Subject: Coding Style cleanup. --- board/v38b/ethaddr.c | 4 +- board/v38b/v38b.c | 1 - doc/README.nand | 3 -- include/configs/V38B.h | 112 ++++++++++++++++++++++++------------------------- 4 files changed, 58 insertions(+), 62 deletions(-) (limited to 'board/v38b/ethaddr.c') diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c index 105608051c..aaa629ef61 100644 --- a/board/v38b/ethaddr.c +++ b/board/v38b/ethaddr.c @@ -118,7 +118,7 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr) crcval = 0; for (i=0; i> 1) | 0x80; else rdat = rdat >> 1; - + udelay(60); /* at least 60 us */ } /* copy the return value */ diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index c56c6c84d2..99fe7dbc3c 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -250,4 +250,3 @@ void hw_watchdog_reset(void) { /* TODO fill this in */ } - diff --git a/doc/README.nand b/doc/README.nand index 2b9a52966c..5279a4f2bc 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -1,9 +1,7 @@ NAND FLASH commands and notes - See NOTE below!!! - # (C) Copyright 2003 # Dave Ellis, SIXNET, dge@sixnetio.com # @@ -209,7 +207,6 @@ the tree until the DoC is ported to use the new NAND support (or boards with DoC will break). - Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 JFFS2 related commands: diff --git a/include/configs/V38B.h b/include/configs/V38B.h index 9b8fc699a9..8eea504742 100644 --- a/include/configs/V38B.h +++ b/include/configs/V38B.h @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along @@ -35,35 +35,35 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ... on V38B board */ -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ... on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ #define CONFIG_NETCONSOLE 1 -#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ -#define CFG_XLB_PIPELINING 1 /* gives better performance */ +#define CFG_XLB_PIPELINING 1 /* gives better performance */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } @@ -97,12 +97,12 @@ #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Supported commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_FAT | \ CFG_CMD_I2C | \ CFG_CMD_IDE | \ @@ -112,7 +112,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAMi | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -123,7 +123,7 @@ /* * Boot low with 16 MB Flash */ -# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT 1 # define CFG_LOWBOOT16 1 /* @@ -131,35 +131,35 @@ */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#define CONFIG_PREBOOT "echo;" \ +#define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "devno=5\0" \ - "hostname=V38B_$(devno)\0" \ - "ipaddr=10.100.99.$(devno)\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.100.10.90\0" \ - "gatewayip=10.100.254.254\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=mpc5200/uImage\0" \ - "bootcmd=run net_nfs\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ - "addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "devno=5\0" \ + "hostname=V38B_$(devno)\0" \ + "ipaddr=10.100.99.$(devno)\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.100.10.90\0" \ + "gatewayip=10.100.254.254\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=mpc5200/uImage\0" \ + "bootcmd=run net_nfs\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ + "addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -196,13 +196,13 @@ */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_BASE 0xFF000000 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ /* * Environment settings @@ -243,7 +243,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 +#define CONFIG_MII 1 /* * GPIO configuration @@ -307,12 +307,12 @@ *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_RESET /* reset for ide supported */ #define CONFIG_IDE_PREINIT #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ @@ -331,13 +331,13 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 -/* Status LED */ +/* Status LED */ -#define CONFIG_STATUS_LED /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ #define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ -- cgit v1.2.3 From ffa150bc90c943ca265170bd1be3f293674dd5c7 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 1 Nov 2006 01:45:46 +0100 Subject: - Fix issues related to the use of ELDK 4 when compiling for MarelV38B: * remove warnings when compiling ethaddr.c * adjust linker script (fixes a crash resulting from incorrect definition of __u_boot_cmd_start) - Some MarelV38B code cleanup. --- board/v38b/ethaddr.c | 91 ++++++++++++++------------------------------------- board/v38b/u-boot.lds | 3 ++ 2 files changed, 28 insertions(+), 66 deletions(-) (limited to 'board/v38b/ethaddr.c') diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c index aaa629ef61..4e2494eee5 100644 --- a/board/v38b/ethaddr.c +++ b/board/v38b/ethaddr.c @@ -1,5 +1,4 @@ /* - * * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -25,48 +24,13 @@ #include #include -#define GPIO_ENABLE (MPC5XXX_WU_GPIO) - -/* Open Drain Emulation Register */ -#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) - -/* Data Direction Register */ -#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) - -/* Data Value Out Register */ -#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) - -/* Interrupt Enable Register */ -#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) - -/* Individual Interrupt Enable Register */ -#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) - -/* Interrupt Type Register */ -#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) - -/* Master Enable Register */ -#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) - -/* Data Input Value Register */ -#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) - -/* Status Register */ -#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) - -#define PSC6_0 0x10000000 -#define WKUP_7 0x80000000 - -/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ -#define GPIO_PIN PSC6_0 +/* For the V38B board the pin is GPIO_PSC_6 */ +#define GPIO_PIN GPIO_PSC6_0 #define NO_ERROR 0 #define ERR_NO_NUMBER 1 #define ERR_BAD_NUMBER 2 -typedef volatile unsigned long GPIO_REG; -typedef GPIO_REG *GPIO_REG_PTR; - static int is_high(void); static int check_device(void); static void io_out(int value); @@ -79,33 +43,34 @@ static void write_byte(unsigned char command); void read_2501_memory(unsigned char *psernum, unsigned char *perr); void board_get_enetaddr(uchar *enetaddr); + static int is_high() { - return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); + return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN); } static void io_out(int value) { if (value) - *((vu_long *) GPIO_DVOR) |= GPIO_PIN; + *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN; else - *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; + *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN; } static void io_input() { - *((vu_long *) GPIO_DDR) &= ~GPIO_PIN; + *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN; udelay(3); /* allow input to settle */ } static void io_output() { - *((vu_long *) GPIO_DDR) |= GPIO_PIN; + *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN; } static void init_gpio() { - *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ + *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ } void read_2501_memory(unsigned char *psernum, unsigned char *perr) @@ -117,8 +82,8 @@ void read_2501_memory(unsigned char *psernum, unsigned char *perr) *perr = 0; crcval = 0; - for (i=0; i