From debb7354d1ea4f694154818df5e5b523f5c1cc1d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 26 Apr 2006 17:58:56 -0500 Subject: Initial support for MPC8641 HPCN board. --- board/mpc8641hpcn/mpc8641hpcn.c | 315 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 315 insertions(+) create mode 100644 board/mpc8641hpcn/mpc8641hpcn.c (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c new file mode 100644 index 0000000000..cdfce6c1fd --- /dev/null +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -0,0 +1,315 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Jeff Brown (jeffrey@freescale.com) + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts("Board: MPC8641HPCN\n"); + +#ifdef CONFIG_PCI + + /* Sri: Note that at this point we will only test on PCI1 + */ + + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + + if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + } + debug ("\n"); + } else { + printf ("PCI-EXPRESS 1: Disabled\n"); + } + +#else + printf("PCI-EXPRESS1: Disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + puts(" DDR: "); + return dram_size; +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. Currently HPCN doesn't have + * SDRAM but we'll leave this here for now + * in case someone changes their mind + */ +#if !defined(CONFIG_MPC8641HPCN) + // sdram_init(); +#endif + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ +#if !defined(CFG_RAMBOOT) + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_0 = CFG_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode_1 = CFG_DDR_MODE_1; + ddr->sdram_mode_2 = CFG_DDR_MODE_2; + ddr->sdram_interval = CFG_DDR_INTERVAL; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000008D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync"); + + udelay(500); + +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg_1 = CFG_DDR_CONTROL; + ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; +#endif + asm("sync; isync"); + + udelay(500); +#endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_fsl86xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc86xxcts_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc86xx_init(struct pci_controller *hose); + + pci_mpc86xx_init(&hose); +#endif /* CONFIG_PCI */ +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } + +} +#endif + +void +after_reloc(ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* now, jump to the main U-Boot board init code */ + board_init_r ((gd_t *)gd, dest_addr); + + /* NOTREACHED */ +} + + + -- cgit v1.2.3 From 5c9efb36a6b5431423f52888a0e3b4b515fe7eca Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 27 Apr 2006 10:15:16 -0500 Subject: Cleanup whitespaces and style issues. Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. --- board/mpc8641hpcn/mpc8641hpcn.c | 33 ++--- board/mpc8641hpcn/oftree.dts | 2 +- cpu/mpc86xx/cpu.c | 262 +++++++++++++++++++--------------------- cpu/mpc86xx/cpu_init.c | 17 ++- cpu/mpc86xx/i2c.c | 68 +++++------ cpu/mpc86xx/interrupts.c | 23 ++-- cpu/mpc86xx/pci.c | 105 ++++++---------- cpu/mpc86xx/spd_sdram.c | 9 +- cpu/mpc86xx/speed.c | 260 +++++++++++++++++++-------------------- cpu/mpc86xx/start.S | 4 +- cpu/mpc86xx/traps.c | 2 - include/configs/MPC8641HPCN.h | 203 +++++++++++++------------------ include/mpc86xx.h | 6 +- 13 files changed, 439 insertions(+), 555 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index cdfce6c1fd..ace6d47fde 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -57,9 +57,6 @@ int checkboard (void) #ifdef CONFIG_PCI - /* Sri: Note that at this point we will only test on PCI1 - */ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile ccsr_pex_t *pex1 = &immap->im_pex1; @@ -70,13 +67,16 @@ int checkboard (void) uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); + if ((io_sel==2 || io_sel==3 || io_sel==5 \ + || io_sel==6 || io_sel==7 || io_sel==0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + debug ("PCI-EXPRESS 1: %s \n", + pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } else { @@ -120,15 +120,6 @@ initdram(int board_type) ddr_enable_ecc(dram_size); #endif - /* - * Initialize SDRAM. Currently HPCN doesn't have - * SDRAM but we'll leave this here for now - * in case someone changes their mind - */ -#if !defined(CONFIG_MPC8641HPCN) - // sdram_init(); -#endif - puts(" DDR: "); return dram_size; } @@ -163,7 +154,7 @@ local_bus_init(void) } #if defined(CFG_DRAM_TEST) -int testdram (void) +int testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -198,10 +189,10 @@ int testdram (void) #if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +long int fixed_sdram(void) { #if !defined(CFG_RAMBOOT) volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/mpc8641hpcn/oftree.dts b/board/mpc8641hpcn/oftree.dts index 6c32ade0ca..8e38047e72 100644 --- a/board/mpc8641hpcn/oftree.dts +++ b/board/mpc8641hpcn/oftree.dts @@ -1,5 +1,5 @@ /* - * MPC8641 HPCn Device Tree Source + * MPC8641 HPCN Device Tree Source * * Copyright 2006 Freescale Semiconductor Inc. * diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index b0fe8abb2c..36da7774ea 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,31 +32,30 @@ #include #endif +extern unsigned long get_board_sys_clk(ulong dummy); -// SS: For debug only, remove after use static __inline__ unsigned long get_dbat3u (void) { - unsigned long dbat3u; - asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); - return dbat3u; + unsigned long dbat3u; + asm volatile("mfspr %0, 542" : "=r" (dbat3u) :); + return dbat3u; } static __inline__ unsigned long get_dbat3l (void) { - unsigned long dbat3l; - asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); - return dbat3l; + unsigned long dbat3l; + asm volatile("mfspr %0, 543" : "=r" (dbat3l) :); + return dbat3l; } static __inline__ unsigned long get_msr (void) { - unsigned long msr; - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; + unsigned long msr; + asm volatile("mfmsr %0" : "=r" (msr) :); + return msr; } -extern unsigned long get_board_sys_clk(ulong dummy); int checkcpu (void) { @@ -66,7 +65,7 @@ int checkcpu (void) uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ - + puts("Freescale PowerPC\n"); pvr = get_pvr(); @@ -74,10 +73,10 @@ int checkcpu (void) major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); - puts ("CPU:\n"); + puts("CPU:\n"); printf(" Core: "); - + switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); @@ -94,7 +93,7 @@ int checkcpu (void) minor = SVR_MIN(svr); puts(" System: "); - switch (ver) { + switch (ver) { case SVR_8641: puts("8641"); break; @@ -113,7 +112,7 @@ int checkcpu (void) printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); - + #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else @@ -134,11 +133,11 @@ int checkcpu (void) printf(" L2: "); if (get_l2cr() & 0x80000000) - printf("Enabled\n"); + printf("Enabled\n"); else - printf("Disabled\n"); - - return (0); + printf("Disabled\n"); + + return 0; } @@ -149,7 +148,7 @@ soft_restart(unsigned long addr) { #ifndef CONFIG_MPC8641HPCN - + /* SRR0 has system reset vector, SRR1 has default MSR value */ /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ @@ -215,7 +214,7 @@ int set_px_sysclk(ulong sysclk) sysclk_s = 0x06; sysclk_r = 0x1F; sysclk_v = 0x3B; - sysclk_aux = 0x06; + sysclk_aux = 0x06; break; case 166: sysclk_s = 0x06; @@ -227,14 +226,14 @@ int set_px_sysclk(ulong sysclk) printf("Unsupported SYSCLK frequency.\n"); return 0; } - + vclkh = (sysclk_s << 5) | sysclk_r ; vclkl = sysclk_v; out8(PIXIS_BASE+PIXIS_VCLKH,vclkh); out8(PIXIS_BASE+PIXIS_VCLKL,vclkl); out8(PIXIS_BASE+PIXIS_AUX,sysclk_aux); - + return 1; } @@ -262,7 +261,7 @@ int set_px_mpxpll(ulong mpxpll) tmp = in8(PIXIS_BASE+PIXIS_VSPEED1); tmp = (tmp & 0xF0) | (val & 0x0F); out8(PIXIS_BASE+PIXIS_VSPEED1,tmp); - + return 1; } @@ -270,9 +269,8 @@ int set_px_corepll(ulong corepll) { u8 tmp; u8 val; - - switch((int)corepll) - { + + switch ((int)corepll) { case 20: val = 0x08; break; @@ -295,11 +293,11 @@ int set_px_corepll(ulong corepll) printf("Unsupported COREPLL ratio.\n"); return 0; } - + tmp = in8(PIXIS_BASE+PIXIS_VSPEED0); tmp = (tmp & 0xE0) | (val & 0x1F); out8(PIXIS_BASE+PIXIS_VSPEED0,tmp); - + return 1; } @@ -311,7 +309,7 @@ void read_from_px_regs(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN0,tmp); } void read_from_px_regs_altbank(int set) @@ -322,7 +320,7 @@ void read_from_px_regs_altbank(int set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); + out8(PIXIS_BASE+PIXIS_VCFGEN1,tmp); } void set_altbank(void) @@ -342,7 +340,7 @@ void set_px_go(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x01; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } void set_px_go_with_watchdog(void) @@ -353,7 +351,7 @@ void set_px_go_with_watchdog(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); tmp = in8(PIXIS_BASE+PIXIS_VCTL); tmp = tmp | 0x09; - out8(PIXIS_BASE+PIXIS_VCTL,tmp); + out8(PIXIS_BASE+PIXIS_VCTL,tmp); } /* This function takes the non-integral cpu:mpx pll ratio @@ -381,11 +379,11 @@ ulong strfractoint(uchar *strptr) no_dec = 1; break; /* Break from loop once the end of string is reached */ } - + intarr[i] = strptr[i]; i++; } - + intarr_len = i; /* Assign length of integer part to intarr_len*/ intarr[i] = '\0'; /* */ @@ -404,14 +402,14 @@ ulong strfractoint(uchar *strptr) i++; j++; } - + decarr_len = j; decarr[j] = '\0'; - + mulconst=1; for(i=0; i 1) - { - cmd = argv[1][1]; - switch(cmd) - { - case 'f': /* reset with frequency changed */ - - if (argc < 5) - goto my_usage; - - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } - else - goto my_usage; - - while(1); /* Not reached */ - - case 'l': - if(argv[2][1] == 'f') - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if(val == 3) - { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - - } - else - goto my_usage; - - while(1); /* Not reached */ - } - else /* Reset from next bank without changing frequencies */ - { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } - - default: - goto my_usage; - } + + if (argc > 1) { + cmd = argv[1][1]; + switch(cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], + NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + } else { + /* Reset from next bank without changing frequencies */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + } + + default: + goto my_usage; + } + my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } - else - out8(PIXIS_BASE+PIXIS_RST,0); - + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } else + out8(PIXIS_BASE+PIXIS_RST,0); + #endif /* !CONFIG_MPC8641HPCN */ - + while(1); /* not reached */ } -/* ------------------------------------------------------------------------- */ - /* * Get timebase clock frequency */ @@ -566,24 +550,21 @@ unsigned long get_tbclk(void) sys_info_t sys_info; get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 3L) / 4L); - + return (sys_info.freqSystemBus + 3L) / 4L; } -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) void watchdog_reset(void) { - } #endif /* CONFIG_WATCHDOG */ -/* ------------------------------------------------------------------------- */ #if defined(CONFIG_DDR_ECC) -void dma_init(void) { +void dma_init(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -593,7 +574,8 @@ void dma_init(void) { return; } -uint dma_check(void) { +uint dma_check(void) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; @@ -609,7 +591,8 @@ uint dma_check(void) { return status; } -int dma_xfer(void *dest, uint count, void *src) { +int dma_xfer(void *dest, uint count, void *src) +{ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_dma_t *dma = &immap->im_dma; @@ -622,6 +605,7 @@ int dma_xfer(void *dest, uint count, void *src) { asm("sync;isync"); return dma_check(); } + #endif /* CONFIG_DDR_ECC */ @@ -631,7 +615,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) u32 *p; ulong clock; int len; - + clock = bd->bi_busfreq; p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); if (p != NULL) @@ -649,7 +633,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); memcpy(p, bd->bi_enetaddr, 6); #endif - + #if defined(CONFIG_MPC86XX_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); memcpy(p, bd->bi_enet1addr, 6); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 582ac6ba95..c816c18974 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -36,13 +36,12 @@ * initialize a bunch of registers */ -void cpu_init_f (void) +void cpu_init_f(void) { DECLARE_GLOBAL_DATA_PTR; volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_lbc_t *memctl = &immap->im_lbc; - //u8 val; - + /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -72,23 +71,21 @@ void cpu_init_f (void) memctl->br1 = CFG_BR1_PRELIM; #endif - //#if !defined(CONFIG_MPC86xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif - //#endif - + #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; memctl->br3 = CFG_BR3_PRELIM; #endif - + #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM) memctl->or4 = CFG_OR4_PRELIM; memctl->br4 = CFG_BR4_PRELIM; #endif - + #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM) memctl->or5 = CFG_OR5_PRELIM; memctl->br5 = CFG_BR5_PRELIM; @@ -123,9 +120,9 @@ void cpu_init_f (void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r (void) +int cpu_init_r(void) { - return (0); + return 0; } diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index c5d4642b9a..f2b4b0f6da 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -74,29 +74,27 @@ i2c_init(int speed, int slaveadd) } static __inline__ int -i2c_wait4bus (void) +i2c_wait4bus(void) { ulong timeval = get_timer (0); - // debug("I2C: Wait for bus\n"); while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) { - if (get_timer (timeval) > TIMEOUT) { + if (get_timer(timeval) > TIMEOUT) { return -1; } } - return 0; + return 0; } static __inline__ int -i2c_wait (int write) +i2c_wait(int write) { u32 csr; ulong timeval = get_timer (0); do { csr = readb(I2CCSR); - if (!(csr & MPC86xx_I2CSR_MIF)) continue; @@ -118,7 +116,7 @@ i2c_wait (int write) } return 0; - } while (get_timer (timeval) < TIMEOUT); + } while (get_timer(timeval) < TIMEOUT); debug("i2c_wait: timed out\n"); return -1; @@ -127,14 +125,13 @@ i2c_wait (int write) static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) { - // debug("I2C: Write Addr\n"); - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX | - (rsta?MPC86xx_I2CCR_RSTA:0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX + | (rsta ? MPC86xx_I2CCR_RSTA : 0), I2CCCR); writeb((dev << 1) | dir, I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) return 0; return 1; @@ -144,14 +141,14 @@ static __inline__ int __i2c_write (u8 *data, int length) { int i; - // debug("I2C: __i2c_write\n"); + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX, I2CCCR); - for (i=0; i < length; i++) { + for (i = 0; i < length; i++) { writeb(data[i], I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) + if (i2c_wait(I2C_WRITE) < 0) break; } @@ -163,33 +160,30 @@ __i2c_read (u8 *data, int length) { int i; - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | ((length == 1) ? MPC86xx_I2CCR_TXAK : 0), I2CCCR); /* dummy read */ readb(I2CCDR); - // debug("length = %d\n", length); - for (i=0; i < length; i++) { - if (i2c_wait (I2C_READ) < 0) + for (i = 0; i < length; i++) { + if (i2c_wait(I2C_READ) < 0) break; /* Generate ack on last next to last byte */ if (i == length - 2) - writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | - MPC86xx_I2CCR_TXAK, + writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA + | MPC86xx_I2CCR_TXAK, I2CCCR); /* Generate stop on last byte */ if (i == length - 1) writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR); - // debug("I2CCR = 0x%08x\n", readb(I2CCCR)); data[i] = readb(I2CCDR); - // debug("data[i] = 0x%08x\n", data[i]); } - // debug("Returning i = %d\n", i); + return i; } @@ -199,19 +193,19 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - if (i2c_write_addr (dev, I2C_READ, 1) == 0) + if (i2c_write_addr(dev, I2C_READ, 1) == 0) goto exit; - i = __i2c_read (data, length); + i = __i2c_read(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -225,16 +219,16 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) int i = 0; u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) + if (i2c_wait4bus() < 0) goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + if (i2c_write_addr(dev, I2C_WRITE, 0) == 0) goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) + if (__i2c_write(&a[4 - alen], alen) != alen) goto exit; - i = __i2c_write (data, length); + i = __i2c_write(data, length); exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); @@ -253,21 +247,21 @@ int i2c_probe (uchar chip) */ udelay(10000); - return i2c_read (chip, 0, 1, (char *)&tmp, 1); + return i2c_read(chip, 0, 1, (char *)&tmp, 1); } uchar i2c_reg_read (uchar i2c_addr, uchar reg) { char buf[1]; - i2c_read (i2c_addr, reg, 1, buf, 1); + i2c_read(i2c_addr, reg, 1, buf, 1); - return (buf[0]); + return buf[0]; } void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) { - i2c_write (i2c_addr, reg, 1, &val, 1); + i2c_write(i2c_addr, reg, 1, &val, 1); } #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 759a30f9f0..b5cd439e53 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -75,7 +75,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return (0); + return 0; } @@ -91,14 +91,14 @@ int interrupt_init (void) decrementer_count = get_tbclk()/CFG_HZ; debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); - - return (0); + + return 0; } @@ -113,7 +113,7 @@ int disable_interrupts (void) ulong msr = get_msr (); set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); + return (msr & MSR_EE) != 0; } @@ -131,7 +131,6 @@ void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ - return; } @@ -139,14 +138,14 @@ void timer_interrupt (struct pt_regs *regs) { /* call cpu specific function from $(CPU)/interrupts.c */ timer_interrupt_cpu (regs); - + timestamp++; ppcDcbf(×tamp); - + /* Restore Decrementer Count */ set_dec (decrementer_count); - + #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) WATCHDOG_RESET (); @@ -169,8 +168,8 @@ void reset_timer (void) } ulong get_timer (ulong base) -{ - return (timestamp - base); +{ + return timestamp - base; } void set_timer (ulong t) @@ -185,13 +184,11 @@ void set_timer (ulong t) void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { - return; } void irq_free_handler(int vec) { - return; } diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c index 9cf5f7ca95..05976bdd4b 100644 --- a/cpu/mpc86xx/pci.c +++ b/cpu/mpc86xx/pci.c @@ -22,7 +22,7 @@ */ /* - * PEX Configuration space access support for MPC85xx PEX Bridge + * PEX Configuration space access support for PEX Bridge */ #include #include @@ -44,24 +44,25 @@ pci_mpc86xx_init(struct pci_controller *hose) ulong addr, data; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ + + if ((io_sel==2 || io_sel==3 || io_sel==5 + || io_sel==6 || io_sel==7 || io_sel==0xF ) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ printf ("PCI-EXPRESS 1: Configured as %s \n", pex1_agent ? "Agent" : "Host"); printf (" Scanning PCI bus"); debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); if (pex1->pme_msg_det) { pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det); + debug (" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); } debug ("\n"); } - - + hose->first_busno = 0; hose->last_busno = 0x7f; @@ -88,36 +89,26 @@ pci_mpc86xx_init(struct pci_controller *hose) */ pci_register_hose(hose); - //#define MPC8548_REV1_PEX12_ERRATA -#ifdef MPC8548_REV1_PEX12_ERRATA - /* can only read/write 4 bytes */ - pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32); - printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32); - - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32); - reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32); -#else pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \ + | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16); - -#endif - /* * Clear non-reserved bits in status register. */ - // pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - // pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + /* + * pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + * pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + */ pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pex1->powar1 = 0x8004401c; /* 512M MEM space */ @@ -129,7 +120,6 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->potar2 = 0x00000000; pex1->potear2 = 0x00000000; - if (!pex1->piwar1) { pex1->pitar1 = 0x00000000; pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff; @@ -140,57 +130,34 @@ pci_mpc86xx_init(struct pci_controller *hose) pex1->pitar2 = 0x00000000; pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff; pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, - - - -/* if (pex1_host) { */ -/* #ifdef MPC8548_REV1_PEX12_ERRATA */ -/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */ -/* #else */ - - - - *(u32 *)(0xf8008000)= 0x80000000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - - pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); -/* #endif */ - - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - *(u32 *)(0xf8008000)= 0x80200000; - debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + * Snoop R/W, 2G */ + *(u32 *)(0xf8008000)= 0x80000000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - - hose->last_busno = pci_hose_scan(hose); - hose->last_busno = 0x21; - debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); - debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); - printf("....PCI scan & enumeration done\n"); + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); -/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */ -/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */ - -/* if (hose->last_busno < 1) { */ -/* hose->last_busno=1; /\*Hack*\/ */ -/* } else { */ -/* hose->last_busno = 0; */ -/* } */ -/*}*/ -/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */ -/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */ + *(u32 *)(0xf8008000)= 0x80200000; + debug("Received data for addr 0x%08lx is 0x%08lx\n", + *(u32*)(0xf8008000), *(u32*)(0xf8008004)); + hose->last_busno = pci_hose_scan(hose); + hose->last_busno = 0x21; + debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno); + debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno); + printf("....PCI scan & enumeration done\n"); } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 9c07f200fb..9ce31d7c6f 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -179,7 +179,7 @@ spd_sdram(void) unsigned int law_size; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; - + /* * Read SPD information. */ @@ -614,7 +614,7 @@ spd_sdram(void) ddr1->timing_cfg_2 = (0 | ((add_lat & 0x7) << 28) /* ADD_LAT */ - | ((cpo & 0x1f) << 23) /* CPO */ + | ((cpo & 0x1f) << 23) /* CPO */ | ((wr_lat & 0x7) << 19) /* WR_LAT */ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ @@ -806,7 +806,7 @@ spd_sdram(void) /* * Memory will be initialized via DMA, or not at all. */ - d_init = 0; + d_init = 0; #endif ddr1->sdram_cfg_2 = (0 @@ -946,8 +946,7 @@ spd_sdram(void) | (LAWAR_SIZE & law_size)); debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); debug("DDR: LARAR1=0x%08x\n", mcm->lawar1); - - + return memsize * 1024 * 1024; } diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 0f5a6388ce..a08ae5f94b 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -33,9 +33,7 @@ unsigned long get_board_sys_clk(ulong dummy); unsigned long get_sysclk_from_px_regs(void); -/* --------------------------------------------------------------- */ - -void get_sys_info (sys_info_t * sysInfo) +void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -43,7 +41,7 @@ void get_sys_info (sys_info_t * sysInfo) plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - + switch(plat_ratio) { case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; @@ -65,72 +63,77 @@ void get_sys_info (sys_info_t * sysInfo) break; } - // printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio); +#if 0 + printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", + sysInfo->freqSystemBus, plat_ratio); +#endif + e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; - switch(e600_ratio) { + + switch (e600_ratio) { case 0x10: - sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: - sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + case 0x19: + sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: - sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; case 0x39: - sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: - sysInfo->freqProcessor = 4*sysInfo->freqSystemBus; + sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus; break; case 0x1d: - sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2; + sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; default: - /* JB - Emulator workaround until real cop is plugged in */ - sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; - //sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + /* JB - Emulator workaround until real cop is plugged in */ + /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } - // printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio); - +#if 0 + printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", + sysInfo->freqProcessor, e600_ratio); +#endif } -/* ------------------------------------------------------------------------- */ - /* * Measure CPU clock speed (core clock GCLK1, GCLK2) - * * (Approx. GCLK frequency in Hz) */ -int get_clocks (void) +int get_clocks(void) { DECLARE_GLOBAL_DATA_PTR; sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; - - if(gd->cpu_clk != 0) return (0); - else return (1); + + if (gd->cpu_clk != 0) + return 0; + else + return 1; } -/* ------------------------------------------------------------------------- */ -/******************************************** + +/* * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq (ulong dummy) + * Return system bus freq in Hz + */ +ulong get_bus_freq(ulong dummy) { ulong val; - sys_info_t sys_info; - get_sys_info (&sys_info); + get_sys_info(&sys_info); val = sys_info.freqSystemBus; return val; @@ -138,111 +141,100 @@ ulong get_bus_freq (ulong dummy) unsigned long get_sysclk_from_px_regs() { - ulong val; - u8 vclkh,vclkl; - - vclkh = in8(PIXIS_BASE+PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE+PIXIS_VCLKL); - - if((vclkh == 0x84) && (vclkl ==0x07)) - { - val = 33000000; - } - if((vclkh == 0x3F) && (vclkl ==0x20)) - { - val = 40000000; - } - if((vclkh == 0x3F) && (vclkl ==0x2A)) - { - val = 50000000; - } - if((vclkh == 0x24) && (vclkl ==0x04)) - { - val = 66000000; - } - if((vclkh == 0x3F) && (vclkl ==0x4B)) - { - val = 83000000; - } - if((vclkh == 0x3F) && (vclkl ==0x5C)) - { - val = 100000000; - } - if((vclkh == 0xDF) && (vclkl ==0x3B)) - { - val = 134000000; - } - if((vclkh == 0xDF) && (vclkl ==0x4B)) - { - val = 166000000; - } - - return val; + ulong val; + u8 vclkh, vclkl; + + vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); + vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); + + if ((vclkh == 0x84) && (vclkl == 0x07)) { + val = 33000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x20)) { + val = 40000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x2A)) { + val = 50000000; + } + if ((vclkh == 0x24) && (vclkl == 0x04)) { + val = 66000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x4B)) { + val = 83000000; + } + if ((vclkh == 0x3F) && (vclkl == 0x5C)) { + val = 100000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x3B)) { + val = 134000000; + } + if ((vclkh == 0xDF) && (vclkl == 0x4B)) { + val = 166000000; + } + + return val; } -/******* From MPC8641HPCN Design Workbook ************ - * + +/* * get_board_sys_clk - * reads the FPGA on board for CONFIG_SYS_CLK_FREQ - * - ********************************************************/ + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ unsigned long get_board_sys_clk(ulong dummy) { - u8 i, go_bit, rd_clks; - ulong val; - - go_bit = in8(PIXIS_BASE+PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if(go_bit) - { - if(rd_clks == 0x1c) - i = in8(PIXIS_BASE+PIXIS_AUX); - else - i = in8(PIXIS_BASE+PIXIS_SPD); - //val = get_sysclk_from_px_regs(); - } - else - i = in8(PIXIS_BASE+PIXIS_SPD); - - i &= 0x07; - - switch(i) - { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; + u8 i, go_bit, rd_clks; + ulong val; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; } diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 531bd0c5fb..0a447a76b7 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -783,12 +783,12 @@ ppcDcbz: dcbz r0,r3 blr -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ /* Function: ppcSync */ /* Description: Processor Synchronize */ /* Input: none. */ /* Output: none. */ -/*------------------------------------------------------------------------------- */ +/*-------------------------------------------------------------------------- */ .globl ppcSync ppcSync: sync diff --git a/cpu/mpc86xx/traps.c b/cpu/mpc86xx/traps.c index fdfc95dfc5..8113dfbcc3 100644 --- a/cpu/mpc86xx/traps.c +++ b/cpu/mpc86xx/traps.c @@ -1,6 +1,4 @@ /* - * linux/arch/ppc/kernel/traps.c - * * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * Modified by Cort Dougan (cort@cs.nmt.edu) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8d2e08851e..76efd7c604 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,6 @@ -/* - * Copyright 2004 Freescale Semiconductor. +/* + * Copyright 2006 Freescale Semiconductor. + * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -22,8 +23,7 @@ */ /* - * mpc8641hpc3 board configuration file - * + * MPC8641HPCN board configuration file * * Make sure you change the MAC address and other network params first, * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. @@ -38,48 +38,38 @@ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#undef DEBUG +#undef DEBUG -//#define RUN_DIAG 1 #ifdef RUN_DIAG #define CFG_DIAG_ADDR 0xff800000 #endif + #define CFG_RESET_ADDRESS 0xfff00100 -//#define CONFIG_PCI +#undef CONFIG_PCI + #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ -/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ALTIVEC 1 -#define CONFIG_ALTIVEC 1 -/*----------------------------------------------------------------------- +/* * L2CR setup -- make sure this is right for your board! */ - -#define CFG_L2 +#define CFG_L2 #define L2_INIT 0 #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ -//#define CONFIG_SYS_CLK_FREQ 33000000 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -/* JB - XXX - Are these available on 86xx? */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -130,10 +120,10 @@ #define CFG_DDR_INTERVAL 0x06090100 #define CFG_DDR_DATA_INIT 0xdeadbeef #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ - #define CFG_DDR_CONTROL2 0x04400000 + #define CFG_DDR_CONTROL2 0x04400000 //Not used in fixed_sdram function @@ -143,20 +133,12 @@ #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done - - - #endif #endif /* - * SDRAM on the Local Bus - */ -//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 + * In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. * However, when u-boot comes up, the flash_init needs hard start addresses @@ -165,15 +147,12 @@ * knows where the flash is and the user can download u-boot code from promjet to * fef00000 <- more intuitive than fe700000. Note that, on switching the boot * location, fef00000 becomes fff00000. -*/ + */ #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ -#define CFG_FLASH_BASE2 0xff800000 +#define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} - -/*Sri: This looks like a good place to init all the Local Bus chip selects*/ - #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ @@ -186,25 +165,24 @@ #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ -#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ -#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -212,11 +190,9 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -/*#define CFG_HPCN_FLASH_CFI_DRIVER */ #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -230,7 +206,7 @@ #undef CONFIG_CLOCKS_IN_MHZ #define CONFIG_L1_INIT_RAM -#undef CFG_INIT_RAM_LOCK +#undef CFG_INIT_RAM_LOCK #ifndef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #else @@ -265,20 +241,22 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 /* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_FLAT_TREE_MAX_SIZE 8192 -#define OF_CPU "PowerPC,8641@0" -#define OF_SOC "soc8641@f8000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ @@ -297,13 +275,10 @@ * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 -//#define CFG_PCI1_MEM_BASE 0xd0000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 -//#define CFG_PCI1_IO_BASE 0xe0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -//#define CFG_PCI1_IO_BUS 0x00000000 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ /* For RTL8139 */ @@ -316,29 +291,18 @@ #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -// #define CFG_PCI1_MEM_BASE 0x80000000 -// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -// #define CFG_PCI1_IO_BASE 0xe2000000 -// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - - #if defined(CONFIG_PCI) - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_SCSI_SCAN_BUS_REVERSE - +#undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -349,7 +313,6 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -371,7 +334,6 @@ #define CONFIG_MPC86XX_TSEC4 1 #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" - #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -389,12 +351,10 @@ /* BAT0 2G Cacheable, non-guarded * 0x0000_0000 2G DDR */ -//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) -//#define CFG_IBAT0L CFG_DBAT0L -//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) +#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE ) +#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP ) +#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) #define CFG_IBAT0U CFG_DBAT0U /* BAT1 1G Cache-inhibited, guarded @@ -402,7 +362,8 @@ * 0xa000_0000 512M PCI-Express 2 Memory ** SS - Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U @@ -410,7 +371,8 @@ /* BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U @@ -418,7 +380,8 @@ /* BAT3 4M Cache-inhibited, guarded * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT3U CFG_DBAT3U @@ -428,7 +391,8 @@ * 0xe300_0000 16M PCI-Express 2 I/0 ** SS - Note that this is at 0xe0000000 */ -#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U @@ -444,12 +408,12 @@ /* BAT6 32M Cache-inhibited, guarded * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U CFG_DBAT6U - #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 #define CFG_IBAT7L 0x00000000 @@ -461,17 +425,17 @@ /* * Environment */ - #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 - #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 - #endif +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -572,24 +536,25 @@ #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 -#define CONFIG_IPADDR 10.82.193.138 +#define CONFIG_IPADDR 10.82.193.138 #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 10.82.193.104 -#define CONFIG_GATEWAYIP 10.82.193.254 -#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 10.82.193.104 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BAUDRATE 115200 @@ -599,7 +564,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=400000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ + "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\ "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 61b527979c..4edeae1647 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2006 Freescale Semiconductor. * Jeffrey Brown (jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) */ @@ -9,7 +9,7 @@ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -/*---------------------------------------------------------------- +/* * l2cr values. Look in config_.h for the actual setup */ #define l2cr 1017 @@ -23,7 +23,7 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- +/* * BAT settings. Look in config_.h for the actual setup */ -- cgit v1.2.3 From 6cfea33477b04b63ed47386ed1629529484c33ba Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 10 May 2006 09:38:06 -0500 Subject: Remove unneeded INIT_RAM_LOCK cache twiddling. Correctly tracks r29 as global data pointer now. Signed-off-by: Haiying Wang --- board/mpc8641hpcn/mpc8641hpcn.c | 11 ----------- common/cmd_bootm.c | 4 ++-- cpu/mpc86xx/start.S | 5 +++-- lib_ppc/board.c | 2 +- 4 files changed, 6 insertions(+), 16 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index ace6d47fde..d02a7eff3c 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -291,16 +291,5 @@ ft_board_setup(void *blob, bd_t *bd) } #endif -void -after_reloc(ulong dest_addr) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* now, jump to the main U-Boot board init code */ - board_init_r ((gd_t *)gd, dest_addr); - - /* NOTREACHED */ -} - diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index fdf7180a19..e5d70fa202 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -809,7 +809,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #ifndef CONFIG_OF_FLAT_TREE -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500) || !defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); #endif @@ -827,7 +827,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ -#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (!defined(CONFIG_E500)||!defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); #endif /* diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 0a447a76b7..b96363151d 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -955,8 +955,9 @@ in_ram: cmplw 0, r3, r4 bne 5b 6: - mr r3, r10 /* Destination Address */ - bl after_reloc + mr r3, r9 /* Init Date pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r /* not reached - end relocate_code */ /*-----------------------------------------------------------------------*/ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 126102bf96..c367b3ef9f 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -676,7 +676,7 @@ void board_init_r (gd_t *id, ulong dest_addr) icache_enable (); /* it's time to enable the instruction cache */ #endif -#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500) +#if defined(CFG_INIT_RAM_LOCK) && (defined(CONFIG_E500) || defined(CONFIG_MPC86xx)) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif -- cgit v1.2.3 From 4d3d729c16c392d2982d3266b659d333c927697d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:24:28 -0500 Subject: Moved mpc8641hpcn_board_reset() out of cpu/ into board/. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 93 +++++++++++++++++++++++++++++++++++++++++ cpu/mpc86xx/cpu.c | 90 +++------------------------------------ 2 files changed, 99 insertions(+), 84 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index d02a7eff3c..dbc9b5e9b8 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -25,6 +25,7 @@ */ #include +#include #include #include #include @@ -35,6 +36,9 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #endif +#include "pixis.h" + + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -292,4 +296,93 @@ ft_board_setup(void *blob, bd_t *bd) #endif +void +mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char cmd; + ulong val; + ulong corepll; + + if (argc > 1) { + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; + + while (1); /* Not reached */ + + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + if (val == 3) { + printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); + } else + goto my_usage; + + while(1); /* Not reached */ + + } else if(argv[2][1] == 'd'){ + /* Reset from next bank without changing frequencies but with watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* Reset from next bank without changing frequency and without watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Resetting board to boot from the other bank....\n"); + set_px_go(); + } + + default: + goto my_usage; + } + + my_usage: + printf("\nUsage: reset cf \n"); + printf(" reset altbank [cf ]\n"); + printf("For example: reset cf 40 2.5 10\n"); + printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); + return; + } else + out8(PIXIS_BASE+PIXIS_RST,0); +} diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 504ba62404..60ce29ccdf 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,7 +32,10 @@ #include #endif -#include "../board/mpc8641hpcn/pixis.h" +#ifdef CONFIG_MPC8641HPCN +extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[]); +#endif int checkcpu (void) @@ -146,9 +149,7 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - char cmd; - ulong addr, val; - ulong corepll; + ulong addr; #ifdef CFG_RESET_ADDRESS addr = CFG_RESET_ADDRESS; @@ -181,86 +182,7 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #else /* CONFIG_MPC8641HPCN */ - if (argc > 1) { - cmd = argv[1][1]; - switch(cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2],NULL,10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], - NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } else - goto my_usage; - - while (1); /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3],NULL,10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - } else if(argv[2][1] == 'd'){ - /* Reset from next bank without changing frequencies but with watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - } else { - /* Reset from next bank without changing frequency and without watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Resetting board to boot from the other bank....\n"); - set_px_go(); - } - - default: - goto my_usage; - } - -my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; - } else - out8(PIXIS_BASE+PIXIS_RST,0); + mpc8641_reset_board(cmdtp, flag, argc, argv); #endif /* !CONFIG_MPC8641HPCN */ -- cgit v1.2.3 From 3d5c5be547445dd3bd2eb7368d80df03ea437970 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 11:39:34 -0500 Subject: Removed unneeded local_bus_init() from 8641HPCN board. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index dbc9b5e9b8..0b08df2039 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -45,7 +45,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); extern long int spd_sdram(void); -void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); @@ -91,11 +90,6 @@ int checkboard (void) printf("PCI-EXPRESS1: Disabled\n"); #endif - /* - * Initialize local bus. - */ - local_bus_init(); - return 0; } @@ -129,34 +123,6 @@ initdram(int board_type) } -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; -} - #if defined(CFG_DRAM_TEST) int testdram(void) { -- cgit v1.2.3 From cb5965fb95b77a49f4e6af95248e0c849f4af03e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 12:44:44 -0500 Subject: White space cleanup. Some 80-column cleanups. Convert printf() to puts() where possible. Use #include "spd_sdram.h" as needed. Enhanced reset command usage message a bit. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 227 +++++++++++++++++++++------------------- cpu/mpc86xx/cpu.c | 27 +++-- 2 files changed, 130 insertions(+), 124 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 0b08df2039..5cd3e9779b 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -38,12 +38,13 @@ extern void ft_cpu_setup(void *blob, bd_t *bd); #include "pixis.h" - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif -extern long int spd_sdram(void); +#if defined(CONFIG_SPD_EEPROM) +#include "spd_sdram.h" +#endif void sdram_init(void); long int fixed_sdram(void); @@ -51,7 +52,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { - return 0; + return 0; } int checkboard (void) @@ -60,34 +61,32 @@ int checkboard (void) #ifdef CONFIG_PCI - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - - - if ((io_sel==2 || io_sel==3 || io_sel==5 \ - || io_sel==6 || io_sel==7 || io_sel==0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ - debug ("PCI-EXPRESS 1: %s \n", - pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug ("\n"); - } else { - printf ("PCI-EXPRESS 1: Disabled\n"); - } + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_pex_t *pex1 = &immap->im_pex1; + + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); + if (pex1->pme_msg_det) { + pex1->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pex1->pme_msg_det); + } + debug ("\n"); + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } #else - printf("PCI-EXPRESS1: Disabled\n"); + puts("PCI-EXPRESS1: Disabled\n"); #endif return 0; @@ -98,7 +97,6 @@ long int initdram(int board_type) { long dram_size = 0; - extern long spd_sdram (void); #if defined(CONFIG_SPD_EEPROM) dram_size = spd_sdram (); @@ -110,7 +108,7 @@ initdram(int board_type) puts(" DDR: "); return dram_size; #endif - + #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. @@ -130,7 +128,7 @@ int testdram(void) uint *pend = (uint *) CFG_MEMTEST_END; uint *p; - printf("SDRAM test phase 1:\n"); + puts("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaaaaaa; @@ -141,7 +139,7 @@ int testdram(void) } } - printf("SDRAM test phase 2:\n"); + puts("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x55555555; @@ -152,7 +150,7 @@ int testdram(void) } } - printf("SDRAM test passed.\n"); + puts("SDRAM test passed.\n"); return 0; } #endif @@ -177,9 +175,9 @@ long int fixed_sdram(void) ddr->sdram_mode_1 = CFG_DDR_MODE_1; ddr->sdram_mode_2 = CFG_DDR_MODE_2; ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; + ddr->sdram_data_init = CFG_DDR_DATA_INIT; ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; + ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; #if defined (CONFIG_DDR_ECC) @@ -187,7 +185,7 @@ long int fixed_sdram(void) ddr->err_sbe = 0x00ff0000; #endif asm("sync;isync"); - + udelay(500); #if defined (CONFIG_DDR_ECC) @@ -198,7 +196,7 @@ long int fixed_sdram(void) ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; #endif asm("sync; isync"); - + udelay(500); #endif return CFG_SDRAM_SIZE * 1024 * 1024; @@ -251,13 +249,12 @@ ft_board_setup(void *blob, bd_t *bd) int len; ft_cpu_setup(blob, bd); - + p = ft_get_prop(blob, "/memory/reg", &len); if (p != NULL) { *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } - } #endif @@ -269,86 +266,96 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong val; ulong corepll; - if (argc > 1) { - cmd = argv[1][1]; - switch (cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); + /* + * No args is a simple reset request. + */ + if (argv <= 0) { + out8(PIXIS_BASE + PIXIS_RST, 0); + /* not reached */ + } + + cmd = argv[1][1]; + switch (cmd) { + case 'f': /* reset with frequency changed */ + if (argc < 5) + goto my_usage; + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); + set_px_go(); + } else + goto my_usage; - val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + while (1); /* Not reached */ - corepll = strfractoint(argv[3]); + case 'l': + if (argv[2][1] == 'f') { + read_from_px_regs(0); + read_from_px_regs_altbank(0); + /* reset with frequency changed */ + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + + corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); if (val == 3) { - printf("Setting registers VCFGEN0 and VCTL\n"); + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); read_from_px_regs(1); - printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); + set_px_go_with_watchdog(); } else goto my_usage; - while (1); /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); - if (val == 3) { - printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while(1); /* Not reached */ - - } else if(argv[2][1] == 'd'){ - /* Reset from next bank without changing frequencies but with watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while(1); /* Not reached */ - - } else { - /* Reset from next bank without changing frequency and without watchdog timer enabled */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; - printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - printf("Resetting board to boot from the other bank....\n"); - set_px_go(); - } + while(1); /* Not reached */ - default: - goto my_usage; + } else if(argv[2][1] == 'd'){ + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); + set_px_go_with_watchdog(); + while(1); /* Not reached */ + + } else { + /* + * Reset from next bank without changing + * frequency and without watchdog timer enabled. + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank....\n"); + set_px_go(); } - my_usage: - printf("\nUsage: reset cf \n"); - printf(" reset altbank [cf ]\n"); - printf("For example: reset cf 40 2.5 10\n"); - printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); - return; + default: + goto my_usage; + } - } else - out8(PIXIS_BASE+PIXIS_RST,0); + my_usage: + puts("\nUsage: reset cf \n"); + puts(" reset altbank [cf ]\n"); + puts(" reset altbank [wd]\n"); + puts("For example: reset cf 40 2.5 10\n"); + puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 60ce29ccdf..fc77d9949f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -1,6 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor - * Jeff Brown (jeffrey@freescale.com) + * Copyright 2006 Freescale Semiconductor + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -55,8 +55,7 @@ int checkcpu (void) minor = PVR_MIN(pvr); puts("CPU:\n"); - - printf(" Core: "); + puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): @@ -112,11 +111,11 @@ int checkcpu (void) printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - printf(" L2: "); + puts(" L2: "); if (get_l2cr() & 0x80000000) - printf("Enabled\n"); + puts("Enabled\n"); else - printf("Disabled\n"); + puts("Disabled\n"); return 0; } @@ -125,7 +124,6 @@ int checkcpu (void) static inline void soft_restart(unsigned long addr) { - #ifndef CONFIG_MPC8641HPCN /* SRR0 has system reset vector, SRR1 has default MSR value */ @@ -137,8 +135,11 @@ soft_restart(unsigned long addr) __asm__ __volatile__ ("rfi"); #else /* CONFIG_MPC8641HPCN */ - out8(PIXIS_BASE+PIXIS_RST,0); + + out8(PIXIS_BASE + PIXIS_RST, 0); + #endif /* !CONFIG_MPC8641HPCN */ + while(1); /* not reached */ } @@ -149,10 +150,10 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr; +#ifndef CONFIG_MPC8641HPCN #ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; + ulong addr = CFG_RESET_ADDRESS; #else /* * note: when CFG_MONITOR_BASE points to a RAM address, @@ -160,11 +161,9 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * address. Better pick an address known to be invalid on your * system and assign it to CFG_RESET_ADDRESS. */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + ulong addr = CFG_MONITOR_BASE - sizeof(ulong); #endif -#ifndef CONFIG_MPC8641HPCN - /* flush and disable I/D cache */ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); -- cgit v1.2.3 From c934f655f9aeca70a5c5f88b465d9e9d57a8d22e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 31 May 2006 13:55:35 -0500 Subject: Review cleanups. Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/config.mk | 2 +- board/mpc8641hpcn/init.S | 26 +++++++--------- board/mpc8641hpcn/mpc8641hpcn.c | 4 +-- board/mpc8641hpcn/u-boot.lds | 2 +- cpu/mpc86xx/Makefile | 4 +-- cpu/mpc86xx/config.mk | 4 +-- cpu/mpc86xx/cpu_init.c | 11 +------ cpu/mpc86xx/i2c.c | 6 ++-- cpu/mpc86xx/interrupts.c | 42 ++++++++++++------------- cpu/mpc86xx/speed.c | 69 ++++++----------------------------------- 10 files changed, 53 insertions(+), 117 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 4bdceec4dc..989a40b015 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -1,5 +1,5 @@ # Copyright 2004 Freescale Semiconductor. -# Modified by Jeff Brown (jeffrey@freescale.com) +# Modified by Jeff Brown # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S index 5f19fdfb6e..69954a81ac 100644 --- a/board/mpc8641hpcn/init.S +++ b/board/mpc8641hpcn/init.S @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -59,7 +59,6 @@ #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) -/*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) /* @@ -72,7 +71,6 @@ #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) -/*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) @@ -86,7 +84,7 @@ #define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) #endif - .section .bootpg, "ax" + .section .bootpg, "ax" .globl law_entry law_entry: lis r7,CFG_CCSRBAR@h @@ -110,8 +108,8 @@ law_entry: stwu r6, 0x20(r4) lis r6,LAWAR2@h - ori r6,r6,LAWAR2@l - stwu r6, 0x20(r5) + ori r6,r6,LAWAR2@l + stwu r6, 0x20(r5) /* LAWBAR3, LAWAR3 */ lis r6,LAWBAR3@h @@ -127,7 +125,7 @@ law_entry: ori r6,r6,LAWBAR4@l stwu r6, 0x20(r4) - lis r6,LAWAR4@h + lis r6,LAWAR4@h ori r6,r6,LAWAR4@l stwu r6, 0x20(r5) /* LAWBAR5, LAWAR5 */ @@ -157,14 +155,14 @@ law_entry: ori r6,r6,LAWAR7@l stwu r6, 0x20(r5) - /* LAWBAR8, LAWAR8 */ - lis r6,LAWBAR8@h - ori r6,r6,LAWBAR8@l - stwu r6, 0x20(r4) + /* LAWBAR8, LAWAR8 */ + lis r6,LAWBAR8@h + ori r6,r6,LAWBAR8@l + stwu r6, 0x20(r4) - lis r6,LAWAR8@h - ori r6,r6,LAWAR8@l - stwu r6, 0x20(r5) + lis r6,LAWAR8@h + ori r6,r6,LAWAR8@l + stwu r6, 0x20(r5) blr diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5cd3e9779b..c6b2a5b3bf 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2002 Scott McNutt @@ -352,7 +352,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto my_usage; } - my_usage: +my_usage: puts("\nUsage: reset cf \n"); puts(" reset altbank [cf ]\n"); puts(" reset altbank [wd]\n"); diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index c5c40e7eb4..b34de8e0ac 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -1,7 +1,7 @@ /* * (C) Copyright 2004, Freescale, Inc. * (C) Copyright 2002,2003, Motorola,Inc. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * * See file CREDITS for list of people who contributed to this * project. diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index 0dd099df6a..ab6255a7df 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -3,7 +3,7 @@ # Xianghua Xiao,X.Xiao@motorola.com # # (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) -# Jeff Brown (Jeffrey@freescale.com) +# Jeff Brown # See file CREDITS for list of people who contributed to this # project. # @@ -30,7 +30,7 @@ LIB = lib$(CPU).a START = start.o #resetvec.o ASOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o i2c.o spd_sdram.o + pci.o i2c.o spd_sdram.o OBJS = $(COBJS) all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 4ef7ace2f4..3c54f4ad39 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -1,6 +1,6 @@ # # (C) Copyright 2004 Freescale Semiconductor. -# Jeff Brown +# Jeff Brown # # See file CREDITS for list of people who contributed to this # project. @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring \ No newline at end of file +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index c816c18974..93b73381f2 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -106,15 +106,6 @@ void cpu_init_f(void) /* enable SYNCBE | ABE bits in HID1 */ set_hid1(get_hid1() | 0x00000C00); - - /* Since the bats have been set up at this point and - * the local bus registers have been initialized, we - * turn on the WDEN bit in PIXIS_VCTL - */ -/* val = in8(PIXIS_BASE+PIXIS_VCTL); */ - /* Set the WDEN */ -/* val |= 0x08; */ -/* out8(PIXIS_BASE+PIXIS_VCTL,val); */ } /* diff --git a/cpu/mpc86xx/i2c.c b/cpu/mpc86xx/i2c.c index f2b4b0f6da..b3ac848a46 100644 --- a/cpu/mpc86xx/i2c.c +++ b/cpu/mpc86xx/i2c.c @@ -7,7 +7,7 @@ * Gleb Natapov * Some bits are taken from linux driver writen by adrian@humboldt.co.uk * - * Modified for MPC86xx by Jeff Brown (jeffrey@freescale.com) + * Modified for MPC86xx by Jeff Brown * * Hardware I2C driver for MPC107 PCI bridge. * @@ -207,7 +207,7 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_read(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); @@ -230,7 +230,7 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) i = __i2c_write(data, length); - exit: +exit: writeb(MPC86xx_I2CCR_MEN, I2CCCR); return !(i == length); diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index b5cd439e53..a8bcb98b81 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -9,7 +9,7 @@ * Xianghua Xiao (X.Xiao@motorola.com) * * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port) - * Jeff Brown (Jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -37,11 +37,10 @@ #include #include -unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ - - +unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; + static __inline__ unsigned long get_msr (void) { unsigned long msr; @@ -75,7 +74,7 @@ static __inline__ void set_dec (unsigned long val) /* interrupt is not supported yet */ int interrupt_init_cpu (unsigned *decrementer_count) { - return 0; + return 0; } @@ -89,14 +88,14 @@ int interrupt_init (void) if (ret) return ret; - decrementer_count = get_tbclk()/CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); + decrementer_count = get_tbclk()/CFG_HZ; + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", (get_tbclk()/1000000), decrementer_count); - set_dec (decrementer_count); + set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); - debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); + debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec()); return 0; } @@ -119,7 +118,7 @@ int disable_interrupts (void) void increment_timestamp(void) { - timestamp++; + timestamp++; } /* @@ -136,15 +135,15 @@ timer_interrupt_cpu (struct pt_regs *regs) void timer_interrupt (struct pt_regs *regs) { - /* call cpu specific function from $(CPU)/interrupts.c */ - timer_interrupt_cpu (regs); + /* call cpu specific function from $(CPU)/interrupts.c */ + timer_interrupt_cpu (regs); - timestamp++; + timestamp++; - ppcDcbf(×tamp); + ppcDcbf(×tamp); - /* Restore Decrementer Count */ - set_dec (decrementer_count); + /* Restore Decrementer Count */ + set_dec (decrementer_count); #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0) @@ -164,17 +163,17 @@ void timer_interrupt (struct pt_regs *regs) void reset_timer (void) { - timestamp = 0; + timestamp = 0; } ulong get_timer (ulong base) { - return timestamp - base; + return timestamp - base; } void set_timer (ulong t) { - timestamp = t; + timestamp = t; } /* @@ -192,11 +191,8 @@ irq_free_handler(int vec) } - -/******************************************************************************* - * +/* * irqinfo - print information about PCI devices,not implemented. - * */ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index a08ae5f94b..5e05ab81f1 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -1,6 +1,6 @@ /* * Copyright 2004 Freescale Semiconductor. - * Jeff Brown (jeffrey@freescale.com) + * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * * (C) Copyright 2000-2002 @@ -29,9 +29,6 @@ #include #include -unsigned long get_board_sys_clk(ulong dummy); -unsigned long get_sysclk_from_px_regs(void); - void get_sys_info (sys_info_t *sysInfo) { @@ -39,11 +36,11 @@ void get_sys_info (sys_info_t *sysInfo) volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; - plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; switch(plat_ratio) { - case 0x0: + case 0x0: sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ; break; case 0x02: @@ -55,19 +52,14 @@ void get_sys_info (sys_info_t *sysInfo) case 0x09: case 0x0a: case 0x0c: - case 0x10: - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - break; + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; default: sysInfo->freqSystemBus = 0; break; } -#if 0 - printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", - sysInfo->freqSystemBus, plat_ratio); -#endif - e600_ratio = (gur->porpllsr) & 0x003f0000; e600_ratio >>= 16; @@ -75,13 +67,13 @@ void get_sys_info (sys_info_t *sysInfo) case 0x10: sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus; break; - case 0x19: + case 0x19: sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2; break; case 0x20: sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; break; - case 0x39: + case 0x39: sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2; break; case 0x28: @@ -90,16 +82,10 @@ void get_sys_info (sys_info_t *sysInfo) case 0x1d: sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2; break; - default: - /* JB - Emulator workaround until real cop is plugged in */ - /* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */ + default: sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } -#if 0 - printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", - sysInfo->freqProcessor, e600_ratio); -#endif } @@ -128,6 +114,7 @@ int get_clocks(void) * get_bus_freq * Return system bus freq in Hz */ + ulong get_bus_freq(ulong dummy) { ulong val; @@ -139,42 +126,6 @@ ulong get_bus_freq(ulong dummy) return val; } -unsigned long get_sysclk_from_px_regs() -{ - ulong val; - u8 vclkh, vclkl; - - vclkh = in8(PIXIS_BASE + PIXIS_VCLKH); - vclkl = in8(PIXIS_BASE + PIXIS_VCLKL); - - if ((vclkh == 0x84) && (vclkl == 0x07)) { - val = 33000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x20)) { - val = 40000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x2A)) { - val = 50000000; - } - if ((vclkh == 0x24) && (vclkl == 0x04)) { - val = 66000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x4B)) { - val = 83000000; - } - if ((vclkh == 0x3F) && (vclkl == 0x5C)) { - val = 100000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x3B)) { - val = 134000000; - } - if ((vclkh == 0xDF) && (vclkl == 0x4B)) { - val = 166000000; - } - - return val; -} - /* * get_board_sys_clk -- cgit v1.2.3 From 684623ce92c5fd32e7db2d6e016945a67c5ffaba Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 22 Jun 2006 08:51:46 -0500 Subject: Fix bug in 8641hpcn reset command with no args. Signed-off-by: Haiying Wang Acked-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index c6b2a5b3bf..2626cccb93 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -269,7 +269,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * No args is a simple reset request. */ - if (argv <= 0) { + if (argc <= 1) { out8(PIXIS_BASE + PIXIS_RST, 0); /* not reached */ } -- cgit v1.2.3 From 239db37c94f7a92941c4465feceb867c609241c5 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 28 Jul 2006 12:41:18 -0400 Subject: Move get_board_sys_clk to board directory --- board/mpc8641hpcn/mpc8641hpcn.c | 64 +++++++++++++++++++++++++++++++++++++++ cpu/mpc86xx/speed.c | 66 ----------------------------------------- 2 files changed, 64 insertions(+), 66 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 2626cccb93..5023c1c97a 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -359,3 +359,67 @@ my_usage: puts("For example: reset cf 40 2.5 10\n"); puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + +/* + * get_board_sys_clk + * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ + */ + +unsigned long get_board_sys_clk(ulong dummy) +{ + u8 i, go_bit, rd_clks; + ulong val = 0; + + go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit &= 0x01; + + rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks &= 0x1C; + + /* + * Only if both go bit and the SCLK bit in VCFGEN0 are set + * should we be using the AUX register. Remember, we also set the + * GO bit to boot from the alternate bank on the on-board flash + */ + + if (go_bit) { + if (rd_clks == 0x1c) + i = in8(PIXIS_BASE + PIXIS_AUX); + else + i = in8(PIXIS_BASE + PIXIS_SPD); + } else { + i = in8(PIXIS_BASE + PIXIS_SPD); + } + + i &= 0x07; + + switch (i) { + case 0: + val = 33000000; + break; + case 1: + val = 40000000; + break; + case 2: + val = 50000000; + break; + case 3: + val = 66000000; + break; + case 4: + val = 83000000; + break; + case 5: + val = 100000000; + break; + case 6: + val = 134000000; + break; + case 7: + val = 166000000; + break; + } + + return val; +} + diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 8088b870a4..e130705378 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -30,72 +30,6 @@ #include -#ifdef MPC8641HPCN -/* - * get_board_sys_clk - * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ - */ - -unsigned long get_board_sys_clk(ulong dummy) -{ - u8 i, go_bit, rd_clks; - ulong val = 0; - - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); - go_bit &= 0x01; - - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); - rd_clks &= 0x1C; - - /* - * Only if both go bit and the SCLK bit in VCFGEN0 are set - * should we be using the AUX register. Remember, we also set the - * GO bit to boot from the alternate bank on the on-board flash - */ - - if (go_bit) { - if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); - else - i = in8(PIXIS_BASE + PIXIS_SPD); - } else { - i = in8(PIXIS_BASE + PIXIS_SPD); - } - - i &= 0x07; - - switch (i) { - case 0: - val = 33000000; - break; - case 1: - val = 40000000; - break; - case 2: - val = 50000000; - break; - case 3: - val = 66000000; - break; - case 4: - val = 83000000; - break; - case 5: - val = 100000000; - break; - case 6: - val = 134000000; - break; - case 7: - val = 166000000; - break; - } - - return val; -} - -#endif - void get_sys_info (sys_info_t *sysInfo) { volatile immap_t *immap = (immap_t *)CFG_IMMR; -- cgit v1.2.3 From 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 22 Aug 2006 12:25:27 -0500 Subject: General indent and whitespace cleanups. --- board/mpc8641hpcn/mpc8641hpcn.c | 69 ++++++------ board/mpc8641hpcn/pixis.c | 21 ++-- board/mpc8641hpcn/sys_eeprom.c | 240 +++++++++++++++++++++------------------- 3 files changed, 170 insertions(+), 160 deletions(-) (limited to 'board/mpc8641hpcn/mpc8641hpcn.c') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5023c1c97a..b2cf4a9566 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -50,12 +50,12 @@ void sdram_init(void); long int fixed_sdram(void); -int board_early_init_f (void) +int board_early_init_f(void) { return 0; } -int checkboard (void) +int checkboard(void) { puts("Board: MPC8641HPCN\n"); @@ -68,7 +68,7 @@ int checkboard (void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) @@ -80,7 +80,7 @@ int checkboard (void) debug(" with errors. Clearing. Now 0x%08x", pex1->pme_msg_det); } - debug ("\n"); + debug("\n"); } else { puts("PCI-EXPRESS 1: Disabled\n"); } @@ -99,9 +99,9 @@ initdram(int board_type) long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); + dram_size = spd_sdram(); #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif #if defined(CFG_RAMBOOT) @@ -122,7 +122,8 @@ initdram(int board_type) #if defined(CFG_DRAM_TEST) -int testdram(void) +int +testdram(void) { uint *pstart = (uint *) CFG_MEMTEST_START; uint *pend = (uint *) CFG_MEMTEST_END; @@ -134,7 +135,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -145,7 +146,7 @@ int testdram(void) for (p = pstart; p < pend; p++) { if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -160,11 +161,12 @@ int testdram(void) /* * Fixed sdram init -- doesn't use serial presence detect. */ -long int fixed_sdram(void) +long int +fixed_sdram(void) { #if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr1; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr1; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -211,28 +213,25 @@ long int fixed_sdram(void) #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_fsl86xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, + {} }; #endif static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP - config_table: pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table, #endif }; -#endif /* CONFIG_PCI */ - +#endif /* CONFIG_PCI */ -void -pci_init_board(void) +void pci_init_board(void) { #ifdef CONFIG_PCI extern void pci_mpc86xx_init(struct pci_controller *hose); @@ -260,7 +259,7 @@ ft_board_setup(void *blob, bd_t *bd) void -mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { char cmd; ulong val; @@ -276,7 +275,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cmd = argv[1][1]; switch (cmd) { - case 'f': /* reset with frequency changed */ + case 'f': /* reset with frequency changed */ if (argc < 5) goto my_usage; read_from_px_regs(0); @@ -294,7 +293,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while (1); /* Not reached */ + while (1) ; /* Not reached */ case 'l': if (argv[2][1] == 'f') { @@ -305,7 +304,8 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) corepll = strfractoint(argv[4]); val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); + val = val + set_px_mpxpll(simple_strtoul(argv[5], + NULL, 10)); if (val == 3) { puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); set_altbank(); @@ -316,9 +316,9 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else goto my_usage; - while(1); /* Not reached */ + while (1) ; /* Not reached */ - } else if(argv[2][1] == 'd'){ + } else if (argv[2][1] == 'd') { /* * Reset from alternate bank without changing * frequencies but with watchdog timer enabled. @@ -330,7 +330,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) read_from_px_regs_altbank(1); puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); set_px_go_with_watchdog(); - while(1); /* Not reached */ + while (1) ; /* Not reached */ } else { /* @@ -339,7 +339,7 @@ mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ read_from_px_regs(0); read_from_px_regs_altbank(0); - if(argc > 2) + if (argc > 2) goto my_usage; puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); set_altbank(); @@ -360,12 +360,14 @@ my_usage: puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); } + /* * get_board_sys_clk * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ */ -unsigned long get_board_sys_clk(ulong dummy) +unsigned long +get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; @@ -422,4 +424,3 @@ unsigned long get_board_sys_clk(ulong dummy) return val; } - diff --git a/board/mpc8641hpcn/pixis.c b/board/mpc8641hpcn/pixis.c index f226b3e8dd..964a17ca08 100644 --- a/board/mpc8641hpcn/pixis.c +++ b/board/mpc8641hpcn/pixis.c @@ -92,13 +92,13 @@ int set_px_sysclk(ulong sysclk) return 0; } - vclkh = (sysclk_s << 5) | sysclk_r ; + vclkh = (sysclk_s << 5) | sysclk_r; vclkl = sysclk_v; out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); - out8(PIXIS_BASE + PIXIS_AUX,sysclk_aux); + out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux); return 1; } @@ -118,7 +118,7 @@ int set_px_mpxpll(ulong mpxpll) case 12: case 14: case 16: - val = (u8)mpxpll; + val = (u8) mpxpll; break; default: printf("Unsupported MPXPLL ratio.\n"); @@ -245,19 +245,16 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* setting VCTL[WDEN] to 0 to disable watch dog */ tmp = in8(PIXIS_BASE + PIXIS_VCTL); - tmp &= ~ 0x08; + tmp &= ~0x08; out8(PIXIS_BASE + PIXIS_VCTL, tmp); return 0; } - U_BOOT_CMD( - diswd, 1, 0, disable_watchdog, - "diswd - Disable watchdog timer \n", - NULL -); - + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL); /* * This function takes the non-integral cpu:mpx pll ratio @@ -295,11 +292,11 @@ ulong strfractoint(uchar *strptr) if (no_dec) { /* Currently needed only for single digit corepll ratios */ - mulconst=10; + mulconst = 10; decval = 0; } else { j = 0; - i++; /* Skipping the decimal point */ + i++; /* Skipping the decimal point */ while ((strptr[i] > 47) && (strptr[i] < 58)) { decarr[j] = strptr[i]; i++; diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c index 733a57f93f..74e2a3d46f 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -29,16 +29,16 @@ #ifdef CFG_ID_EEPROM typedef struct { - unsigned char id[4]; /* 0x0000 - 0x0003 */ - unsigned char sn[12]; /* 0x0004 - 0x000F */ - unsigned char errata[5];/* 0x0010 - 0x0014 */ - unsigned char date[7]; /* 0x0015 - 0x001a */ - unsigned char res_1[37];/* 0x001b - 0x003f */ - unsigned char tab_size; /* 0x0040 */ - unsigned char tab_flag; /* 0x0041 */ - unsigned char mac[8][6];/* 0x0042 - 0x0071 */ - unsigned char res_2[126];/* 0x0072 - 0x00ef */ - unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ + unsigned char id[4]; /* 0x0000 - 0x0003 */ + unsigned char sn[12]; /* 0x0004 - 0x000F */ + unsigned char errata[5]; /* 0x0010 - 0x0014 */ + unsigned char date[7]; /* 0x0015 - 0x001a */ + unsigned char res_1[37]; /* 0x001b - 0x003f */ + unsigned char tab_size; /* 0x0040 */ + unsigned char tab_flag; /* 0x0041 */ + unsigned char mac[8][6]; /* 0x0042 - 0x0071 */ + unsigned char res_2[126]; /* 0x0072 - 0x00ef */ + unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */ } EEPROM_data; static EEPROM_data mac_data; @@ -48,30 +48,34 @@ int mac_show(void) int i; unsigned char ethaddr[8][18]; - printf("ID %c%c%c%c\n", mac_data.id[0],\ - mac_data.id[1],\ - mac_data.id[2],\ - mac_data.id[3]); - printf("Errata %c%c%c%c%c\n", mac_data.errata[0],\ - mac_data.errata[1],\ - mac_data.errata[2],\ - mac_data.errata[3],\ - mac_data.errata[4]); - printf("Date %c%c%c%c%c%c%c\n", mac_data.date[0],\ - mac_data.date[1],\ - mac_data.date[2],\ - mac_data.date[3],\ - mac_data.date[4],\ - mac_data.date[5],\ - mac_data.date[6]); + printf("ID %c%c%c%c\n", + mac_data.id[0], + mac_data.id[1], + mac_data.id[2], + mac_data.id[3]); + printf("Errata %c%c%c%c%c\n", + mac_data.errata[0], + mac_data.errata[1], + mac_data.errata[2], + mac_data.errata[3], + mac_data.errata[4]); + printf("Date %c%c%c%c%c%c%c\n", + mac_data.date[0], + mac_data.date[1], + mac_data.date[2], + mac_data.date[3], + mac_data.date[4], + mac_data.date[5], + mac_data.date[6]); for (i = 0; i < 8; i++) { - sprintf(ethaddr[i],"%02x:%02x:%02x:%02x:%02x:%02x",\ - mac_data.mac[i][0],\ - mac_data.mac[i][1],\ - mac_data.mac[i][2],\ - mac_data.mac[i][3],\ - mac_data.mac[i][4],\ - mac_data.mac[i][5]); + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], + mac_data.mac[i][5]); printf("MAC %d %s\n", i, ethaddr[i]); } @@ -85,7 +89,7 @@ int mac_show(void) int mac_read(void) { - int ret,length; + int ret, length; unsigned int crc = 0; unsigned char dev = ID_EEPROM_ADDR, *data; @@ -98,12 +102,12 @@ int mac_read(void) data = (unsigned char *)(&mac_data); printf("Check CRC on reading ..."); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { - printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",mac_data.crc,crc); + printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n", + mac_data.crc, crc); return -1; - } - else { + } else { printf("CRC OK\n"); mac_show(); } @@ -114,94 +118,97 @@ int mac_prog(void) { int ret, i, length; unsigned int crc = 0; - unsigned char dev = ID_EEPROM_ADDR,*ptr; - unsigned char * eeprom_data = (unsigned char *)(&mac_data); + unsigned char dev = ID_EEPROM_ADDR, *ptr; + unsigned char *eeprom_data = (unsigned char *)(&mac_data); for (i = 0; i < sizeof(mac_data.res_1); i++) mac_data.res_1[i] = 0; - for (i = 0;i < sizeof(mac_data.res_2); i++) + for (i = 0; i < sizeof(mac_data.res_2); i++) mac_data.res_2[i] = 0; length = sizeof(EEPROM_data); - crc = crc32 (crc, eeprom_data, length-4); + crc = crc32(crc, eeprom_data, length - 4); mac_data.crc = crc; for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) { - ret = i2c_write(dev, i, 1, ptr, (length-i) <8 ? (length-i) : 8); - udelay(5000); /* 5ms write cycle timing */ + ret = + i2c_write(dev, i, 1, ptr, + (length - i) < 8 ? (length - i) : 8); + udelay(5000); /* 5ms write cycle timing */ if (ret) break; } if (ret) { printf("Programming failed.\n"); return -1; - } - else { - printf("Programming %d bytes. Reading back ...\n",length); + } else { + printf("Programming %d bytes. Reading back ...\n", length); mac_read(); } return 0; } -int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; char cmd = 's'; unsigned long long mac_val; - if(i2c_probe(ID_EEPROM_ADDR) != 0) + if (i2c_probe(ID_EEPROM_ADDR) != 0) return -1; - if(argc>1) { + if (argc > 1) { cmd = argv[1][0]; switch (cmd) { - case 'r': /* display */ - mac_read(); - break; - case 's': /* save */ - mac_prog(); - break; - case 'i': /* id */ - for (i=0; i<4; i++) { - mac_data.id[i] = argv[2][i]; - } - break; - case 'n': /* serial number */ - for (i=0; i<12; i++) { - mac_data.sn[i] = argv[2][i]; - } - break; - case 'e': /* errata */ - for (i=0; i<5; i++) { - mac_data.errata[i] = argv[2][i]; - } - break; - case 'd': /* date */ - for (i=0; i<7; i++) { - mac_data.date[i] = argv[2][i]; - } - break; - case 'p': /* number of ports */ - mac_data.tab_size = (unsigned char)simple_strtoul(argv[2],NULL,16); - break; - case '0': /* mac 0 */ - case '1': /* mac 1 */ - case '2': /* mac 2 */ - case '3': /* mac 3 */ - case '4': /* mac 4 */ - case '5': /* mac 5 */ - case '6': /* mac 6 */ - case '7': /* mac 7 */ - mac_val = simple_strtoull(argv[2],NULL,16); - for (i=0; i<6; i++) { - mac_data.mac[cmd-'0'][i] = *((unsigned char *)(((unsigned int)(&mac_val))+i+2)); - } - break; - case 'h': /* help */ - default: - printf ("Usage:\n%s\n", cmdtp->usage); - break; + case 'r': /* display */ + mac_read(); + break; + case 's': /* save */ + mac_prog(); + break; + case 'i': /* id */ + for (i = 0; i < 4; i++) { + mac_data.id[i] = argv[2][i]; + } + break; + case 'n': /* serial number */ + for (i = 0; i < 12; i++) { + mac_data.sn[i] = argv[2][i]; + } + break; + case 'e': /* errata */ + for (i = 0; i < 5; i++) { + mac_data.errata[i] = argv[2][i]; + } + break; + case 'd': /* date */ + for (i = 0; i < 7; i++) { + mac_data.date[i] = argv[2][i]; + } + break; + case 'p': /* number of ports */ + mac_data.tab_size = + (unsigned char)simple_strtoul(argv[2], NULL, 16); + break; + case '0': /* mac 0 */ + case '1': /* mac 1 */ + case '2': /* mac 2 */ + case '3': /* mac 3 */ + case '4': /* mac 4 */ + case '5': /* mac 5 */ + case '6': /* mac 6 */ + case '7': /* mac 7 */ + mac_val = simple_strtoull(argv[2], NULL, 16); + for (i = 0; i < 6; i++) { + mac_data.mac[cmd - '0'][i] = + *((unsigned char *) + (((unsigned int)(&mac_val)) + i + 2)); + } + break; + case 'h': /* help */ + default: + printf("Usage:\n%s\n", cmdtp->usage); + break; } - } - else { + } else { mac_show(); } return 0; @@ -209,36 +216,41 @@ int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int mac_read_from_eeprom(void) { - int length,i; - unsigned char dev = ID_EEPROM_ADDR, *data, ethaddr[4][18], enetvar[32]; + int length, i; + unsigned char dev = ID_EEPROM_ADDR; + unsigned char *data; + unsigned char ethaddr[4][18]; + unsigned char enetvar[32]; unsigned int crc = 0; length = sizeof(EEPROM_data); - if(i2c_read (dev, 0, 1, (unsigned char *)(&mac_data), length)) { + if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) { printf("Read failed.\n"); return -1; } data = (unsigned char *)(&mac_data); - crc = crc32(crc, data, length-4); + crc = crc32(crc, data, length - 4); if (crc != mac_data.crc) { return -1; - } - else { - for(i=0; i<4; i++) { - if(memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf(ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", \ - mac_data.mac[i][0], \ - mac_data.mac[i][1], \ - mac_data.mac[i][2], \ - mac_data.mac[i][3], \ - mac_data.mac[i][4], \ + } else { + for (i = 0; i < 4; i++) { + if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { + sprintf(ethaddr[i], + "%02x:%02x:%02x:%02x:%02x:%02x", + mac_data.mac[i][0], + mac_data.mac[i][1], + mac_data.mac[i][2], + mac_data.mac[i][3], + mac_data.mac[i][4], mac_data.mac[i][5]); - sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + sprintf(enetvar, + i ? "eth%daddr" : "ethaddr", + i); setenv(enetvar, ethaddr[i]); } } } return 0; } -#endif /* CFG_ID_EEPROM */ +#endif /* CFG_ID_EEPROM */ -- cgit v1.2.3