From a8571337d78093d2aff25add22df5cdc4e30f8a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 May 2021 21:34:20 -0400 Subject: ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain Signed-off-by: Tom Rini --- board/freescale/mpc8541cds/ddr.c | 53 ---------------------------------------- 1 file changed, 53 deletions(-) delete mode 100644 board/freescale/mpc8541cds/ddr.c (limited to 'board/freescale/mpc8541cds/ddr.c') diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c deleted file mode 100644 index 05c56a85d2..0000000000 --- a/board/freescale/mpc8541cds/ddr.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 6; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} -- cgit v1.2.3