From 06ad970b53a3d6aa122685e6142a04908434a8ef Mon Sep 17 00:00:00 2001 From: Darwin Dingel Date: Tue, 25 Oct 2016 09:48:01 +1300 Subject: powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907 Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham Signed-off-by: Darwin Dingel Cc: York Sun [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun --- arch/powerpc/include/asm/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/processor.h') diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fbf72bb7c6..81bae6f008 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -501,6 +501,7 @@ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -- cgit v1.2.3