From 9a511bd6a372936e5f22031de1b4b13ae50212dc Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 29 Oct 2012 19:00:41 -0500 Subject: powerpc/mpc85xx: add comma before "already enabled" Now outputs like this: L2: 512 KB already enabled, moving to 0xf8f80000 rather than this: L2: 512 KB already enabledmoving to 0xf8f80000 Signed-off-by: Scott Wood Cc: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f01804bbb9..705c16c558 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -470,7 +470,7 @@ int cpu_init_r(void) && l2srbar >= CONFIG_SYS_FLASH_BASE) { l2srbar = CONFIG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); } #endif /* CONFIG_SYS_INIT_L2_ADDR */ puts("\n"); -- cgit v1.2.3 From 2a5fcb835f6e976ed0eb34c413d40f2d4a5e8d1f Mon Sep 17 00:00:00 2001 From: York Sun Date: Sun, 28 Oct 2012 08:12:54 +0000 Subject: powerpc/mpc85xx: Temporary fix for spin table backward compatibility Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 12 +++++++++++ arch/powerpc/cpu/mpc85xx/release.S | 35 ++++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ 3 files changed, 52 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 705c16c558..9c1887f592 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,6 +350,10 @@ int cpu_init_r(void) #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + extern int spin_table_compat; + const char *spin; +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) @@ -395,6 +399,14 @@ int cpu_init_r(void) } #endif +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + puts ("L2: "); #if defined(CONFIG_L2_CACHE) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 4ba44a9028..1f76925dc1 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -351,6 +351,13 @@ __secondary_reset_vector: .align L1_CACHE_SHIFT .global __second_half_boot_page __second_half_boot_page: +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + lis r3,(spin_table_compat - __second_half_boot_page)@h + ori r3,r3,(spin_table_compat - __second_half_boot_page)@l + add r3,r3,r11 /* r11 has the address of __second_half_boot_page */ + lwz r14,0(r3) +#endif + #define EPAPR_MAGIC 0x45504150 #define ENTRY_ADDR_UPPER 0 #define ENTRY_ADDR_LOWER 4 @@ -383,7 +390,24 @@ __second_half_boot_page: stw r8,ENTRY_ADDR_LOWER(r10) /* spin waiting for addr */ -3: lwz r4,ENTRY_ADDR_LOWER(r10) +3: +/* + * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled + * memory. Old OS may not work with this change. A patch is waiting to be + * accepted for Linux kernel. Other OS needs similar fix to spin table. + * For OSes with old spin table code, we can enable this temporary fix by + * setting environmental variable "spin_table_compat". For new OSes, set + * "spin_table_compat=no". After Linux is fixed, we can remove this macro + * and related code. For now, it is enabled by default. + */ +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + cmpwi r14,0 + beq 4f + dcbf 0, r10 + sync +4: +#endif + lwz r4,ENTRY_ADDR_LOWER(r10) andi. r11,r4,1 bne 3b isync @@ -460,5 +484,14 @@ __second_half_boot_page: .globl __spin_table __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + .align L1_CACHE_SHIFT + .global spin_table_compat +spin_table_compat: + .long 1 + +#endif + __spin_table_end: .space 4096 - (__spin_table_end - __spin_table) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 61dd061427..d1c1e0681a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -27,6 +27,12 @@ #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." #endif +/* + * This macro should be removed when we no longer care about backwards + * compatibility with older operating systems. + */ +#define CONFIG_PPC_SPINTABLE_COMPATIBLE + #define FSL_DDR_VER_4_7 47 /* Number of TLB CAM entries we have on FSL Book-E chips */ -- cgit v1.2.3 From afbfdf545090472b734367ac2c874bfbe8928790 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 8 Nov 2012 12:33:39 +0000 Subject: powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE Fix a bug introduced by this patch powerpc/mpc85xx: Temporary fix for spin table backward compatibility Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in cpu_init.c. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 9c1887f592..d1155e8126 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,7 +350,7 @@ int cpu_init_r(void) #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif -#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) extern int spin_table_compat; const char *spin; #endif @@ -399,7 +399,7 @@ int cpu_init_r(void) } #endif -#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) spin = getenv("spin_table_compat"); if (spin && (*spin == 'n')) spin_table_compat = 0; -- cgit v1.2.3