From 2e2ed3f4ff5f21a5c39394c55d361e826238ce2d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 31 Jul 2012 05:38:56 -0400 Subject: Blackfin: adjust asm constraints with NMI workaround Newer gcc versions will sometimes use a Preg when "r" constraints, but that'll fail if we use an Ireg in the assignment. So force the code to always use a Dreg. This also fixes early boot crashes for older Blackfin parts when compiled with gcc-4.5. This version ends up selecting the same register for the input and output variables which corrupts the output assignment triggering an exception. P2 = 0xffe02008; /* EVT2 */ R0 = RETS; CALL 1f; RTN; 1: P2 = RETS; <-- BAD RETS = R0; [P2] = P2; <-- BAD Signed-off-by: Mike Frysinger Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/initcode.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 1a066806d1..e8ea0ba66a 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -262,7 +262,8 @@ program_nmi_handler(void) "%1 = RETS;" /* Load addr of NMI handler */ "RETS = %0;" /* Restore RETS */ "[%2] = %1;" /* Write NMI handler */ - : "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2) + : "=d"(tmp1), "=d"(tmp2) + : "ab"(EVT2) ); } -- cgit v1.2.3 From 79f2b3992f52334b510214c6b1b60c4200133658 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 5 Feb 2013 19:10:34 +0800 Subject: blackfin: Set correct early debug serial baudrate. Calculate the early uart clock from the system clock registers set by the bootrom other than the predefine uboot clock macros. Split the early baudrate setting function and the normal baudrate setting one. Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/initcode.c | 43 ++++++++--------------- arch/blackfin/cpu/serial.c | 12 +++++-- arch/blackfin/cpu/serial1.h | 43 +++++++++-------------- arch/blackfin/cpu/serial4.h | 27 +++++--------- arch/blackfin/include/asm/clock.h | 74 +++++++++++++++++++++++++++++++++++++++ arch/blackfin/lib/clocks.c | 12 +------ 6 files changed, 123 insertions(+), 88 deletions(-) create mode 100644 arch/blackfin/include/asm/clock.h (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index e8ea0ba66a..5c12726d77 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -194,15 +194,8 @@ static inline void serial_init(void) #endif if (BFIN_DEBUG_EARLY_SERIAL) { - int enabled = serial_early_enabled(uart_base); - serial_early_init(uart_base); - - /* If the UART is off, that means we need to program - * the baud rate ourselves initially. - */ - if (!enabled) - serial_early_set_baud(uart_base, CONFIG_BAUDRATE); + serial_early_set_baud(uart_base, CONFIG_BAUDRATE); } } @@ -714,37 +707,29 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) __attribute__((always_inline)) static inline void update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) { - serial_putc('a'); - /* Since we've changed the SCLK above, we may need to update * the UART divisors (UART baud rates are based on SCLK). * Do the division by hand as there are no native instructions * for dividing which means we'd generate a libgcc reference. */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { - unsigned int sdivR, vcoR; - int dividend = sdivB * divB * vcoR; - int divisor = vcoB * sdivR; - unsigned int quotient; + unsigned int sdivR, vcoR; + unsigned int dividend = sdivB * divB * vcoR; + unsigned int divisor = vcoB * sdivR; + unsigned int quotient; - serial_putc('b'); + serial_putc('a'); #ifdef __ADSPBF60x__ - sdivR = bfin_read_CGU_DIV(); - sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7); - vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f; + sdivR = bfin_read_CGU_DIV(); + sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7); + vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f; #else - sdivR = bfin_read_PLL_DIV() & 0xf; - vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; + sdivR = bfin_read_PLL_DIV() & 0xf; + vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; #endif - - for (quotient = 0; dividend > 0; ++quotient) - dividend -= divisor; - serial_early_put_div(quotient - ANOMALY_05000230); - serial_putc('c'); - } - - serial_putc('d'); + quotient = early_division(dividend, divisor); + serial_early_put_div(quotient - ANOMALY_05000230); + serial_putc('c'); } __attribute__((always_inline)) static inline void diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c index 9847e9f2c5..36d2a5c8e4 100644 --- a/arch/blackfin/cpu/serial.c +++ b/arch/blackfin/cpu/serial.c @@ -195,6 +195,14 @@ static void uart_loop(uint32_t uart_base, int state) #endif +static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud) +{ + uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16) + - ANOMALY_05000230; + + /* Program the divisor to get the baud rate we want */ + serial_set_divisor(uart_base, divisor); +} #ifdef CONFIG_SYS_BFIN_UART static void uart_puts(uint32_t uart_base, const char *s) @@ -209,7 +217,7 @@ static int uart##n##_init(void) \ const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \ peripheral_request_list(pins, "bfin-uart"); \ uart_init(MMR_UART(n)); \ - serial_early_set_baud(MMR_UART(n), gd->baudrate); \ + __serial_set_baud(MMR_UART(n), gd->baudrate); \ uart_lsr_clear(MMR_UART(n)); \ return 0; \ } \ @@ -221,7 +229,7 @@ static int uart##n##_uninit(void) \ \ static void uart##n##_setbrg(void) \ { \ - serial_early_set_baud(MMR_UART(n), gd->baudrate); \ + __serial_set_baud(MMR_UART(n), gd->baudrate); \ } \ \ static int uart##n##_getc(void) \ diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h index a20175bc7f..52f1c62eb9 100644 --- a/arch/blackfin/cpu/serial1.h +++ b/arch/blackfin/cpu/serial1.h @@ -15,6 +15,8 @@ #ifndef __ASSEMBLY__ +#include + #define MMR_UART(n) _PASTE_UART(n, UART, DLL) #ifdef UART_DLL # define UART0_DLL UART_DLL @@ -229,19 +231,6 @@ static inline void serial_early_do_portmux(void) SSYNC(); } -__attribute__((always_inline)) -static inline uint32_t uart_sclk(void) -{ -#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) - /* We cannot use get_sclk() early on as it uses - * caches in external memory - */ - return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV; -#else - return get_sclk(); -#endif -} - __attribute__((always_inline)) static inline int uart_init(uint32_t uart_base) { @@ -275,21 +264,8 @@ static inline int serial_early_uninit(uint32_t uart_base) } __attribute__((always_inline)) -static inline int serial_early_enabled(uint32_t uart_base) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) { - return bfin_read(&pUART->gctl) & UCEN; -} - -__attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) -{ - /* Translate from baud into divisor in terms of SCLK. The - * weird multiplication is to make sure we over sample just - * a little rather than under sample the incoming signals. - */ - uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) - - ANOMALY_05000230; - /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); @@ -304,6 +280,19 @@ static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) SSYNC(); } +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + /* Translate from baud into divisor in terms of SCLK. The + * weird multiplication is to make sure we over sample just + * a little rather than under sample the incoming signals. + */ + uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8), + baud * 16) - ANOMALY_05000230; + + serial_set_divisor(uart_base, divisor); +} + __attribute__((always_inline)) static inline void serial_early_put_div(uint16_t divisor) { diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h index 887845c186..65483960b9 100644 --- a/arch/blackfin/cpu/serial4.h +++ b/arch/blackfin/cpu/serial4.h @@ -15,6 +15,8 @@ #ifndef __ASSEMBLY__ +#include + #define MMR_UART(n) _PASTE_UART(n, UART, REVID) #define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) @@ -83,20 +85,6 @@ static inline void serial_early_do_portmux(void) SSYNC(); } -__attribute__((always_inline)) -static inline uint32_t uart_sclk(void) -{ -#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL) - /* We cannot use get_sclk() early on as it uses caches in - * external memory - */ - return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV / - CONFIG_SCLK0_DIV; -#else - return get_sclk0(); -#endif -} - __attribute__((always_inline)) static inline int uart_init(uint32_t uart_base) { @@ -127,19 +115,20 @@ static inline int serial_early_uninit(uint32_t uart_base) } __attribute__((always_inline)) -static inline int serial_early_enabled(uint32_t uart_base) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) { - return bfin_read(&pUART->control) & UEN; + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->clock, divisor); + SSYNC(); } __attribute__((always_inline)) static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) { - uint32_t divisor = uart_sclk() / (baud * 16); + uint16_t divisor = early_division(early_get_uart_clk(), baud * 16); /* Program the divisor to get the baud rate we want */ - bfin_write(&pUART->clock, divisor); - SSYNC(); + serial_set_divisor(uart_base, divisor); } __attribute__((always_inline)) diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h new file mode 100644 index 0000000000..df6cd68171 --- /dev/null +++ b/arch/blackfin/include/asm/clock.h @@ -0,0 +1,74 @@ + +/* + * Copyright (C) 2012 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include +#ifdef PLL_CTL +#include +# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) +#else +#include +# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) +# define bfin_read_PLL_CTL() bfin_read_CGU_CTL() +# define bfin_read_PLL_DIV() bfin_read_CGU_DIV() +# define SSEL SYSSEL +# define SSEL_P SYSSEL_P +#endif + +__attribute__((always_inline)) +static inline uint32_t early_division(uint32_t dividend, uint32_t divisor) +{ + uint32_t quotient; + uint32_t i, j; + + for (quotient = 1, i = 1; dividend > divisor; ++i) { + j = divisor << i; + if (j > dividend || (j & 0x80000000)) { + --i; + quotient += (1 << i); + dividend -= (divisor << i); + i = 0; + } + } + + return quotient; +} + +__attribute__((always_inline)) +static inline uint32_t early_get_uart_clk(void) +{ + uint32_t msel, pll_ctl, vco; + uint32_t div, ssel, sclk, uclk; + + pll_ctl = bfin_read_PLL_CTL(); + msel = (pll_ctl & MSEL) >> MSEL_P; + if (msel == 0) + msel = (MSEL >> MSEL_P) + 1; + + vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel; + sclk = vco; + if (!pll_is_bypassed()) { + div = bfin_read_PLL_DIV(); + ssel = (div & SSEL) >> SSEL_P; + sclk = early_division(vco, ssel); + } + uclk = sclk; +#ifdef CGU_DIV + ssel = (div & S0SEL) >> S0SEL_P; + uclk = early_division(sclk, ssel); +#endif + return uclk; +} + +#ifdef CGU_DIV +# define get_uart_clk get_sclk0 +#else +# define get_uart_clk get_sclk +#endif + +#endif diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c index d852f5ebed..97795e11ac 100644 --- a/arch/blackfin/lib/clocks.c +++ b/arch/blackfin/lib/clocks.c @@ -7,17 +7,7 @@ */ #include -#include - -#ifdef PLL_CTL -# include -# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) -#else -# include -# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) -# define bfin_read_PLL_CTL() bfin_read_CGU_CTL() -# define bfin_read_PLL_DIV() bfin_read_CGU_DIV() -#endif +#include /* Get the voltage input multiplier */ u_long get_vco(void) -- cgit v1.2.3 From ab80b6595765a01f774ad2a29fde8b0c325533ac Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 30 Nov 2012 17:39:32 +0800 Subject: blackfin: Correct early serial mess output in BYPASS boot mode. The early serial should not be configured again in initcode() for BYPASS boot mode and in start() for the other LDR boot modes. In BYPASS boot mode, the start up code is located in Nor flash address other than the DRAM address defined in link script. The code embedded string can't be addressed by its compile time symbol. Calculate it according to the flash offset. Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/initcode.c | 2 ++ arch/blackfin/cpu/serial.h | 17 +++++++++++++++-- arch/blackfin/cpu/serial1.h | 5 +++++ arch/blackfin/include/asm/clock.h | 6 +++++- 4 files changed, 27 insertions(+), 3 deletions(-) (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 5c12726d77..4b10b6c6b2 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -193,10 +193,12 @@ static inline void serial_init(void) } #endif +#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS if (BFIN_DEBUG_EARLY_SERIAL) { serial_early_init(uart_base); serial_early_set_baud(uart_base, CONFIG_BAUDRATE); } +#endif } __attribute__((always_inline)) diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 9200339668..d67fd81c09 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -78,19 +78,31 @@ static inline void serial_early_puts(const char *s) #else .macro serial_early_init -#ifdef CONFIG_DEBUG_EARLY_SERIAL +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && defined(BFIN_BOOT_BYPASS) call _serial_initialize; #endif .endm .macro serial_early_set_baud -#ifdef CONFIG_DEBUG_EARLY_SERIAL +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && defined(BFIN_BOOT_BYPASS) R0.L = LO(CONFIG_BAUDRATE); R0.H = HI(CONFIG_BAUDRATE); call _serial_set_baud; #endif .endm +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS +#define update_serial_early_string_addr \ + R1.L = _start; \ + R1.H = _start; \ + R0 = R0 - R1; \ + R1.L = 0; \ + R1.H = 0x2000; \ + R0 = R0 + R1; +#else +#define update_serial_early_string_addr +#endif + /* Since we embed the string right into our .text section, we need * to find its address. We do this by getting our PC and adding 2 * bytes (which is the length of the jump instruction). Then we @@ -108,6 +120,7 @@ static inline void serial_early_puts(const char *s) .previous; \ R0.L = 7b; \ R0.H = 7b; \ + update_serial_early_string_addr \ call _serial_puts; #else # define serial_early_puts(str) diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h index 52f1c62eb9..467d3817f1 100644 --- a/arch/blackfin/cpu/serial1.h +++ b/arch/blackfin/cpu/serial1.h @@ -287,8 +287,13 @@ static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) * weird multiplication is to make sure we over sample just * a little rather than under sample the incoming signals. */ +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS + uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16) + - ANOMALY_05000230; +#else uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8), baud * 16) - ANOMALY_05000230; +#endif serial_set_divisor(uart_base, divisor); } diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index df6cd68171..f1fcd40499 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -10,7 +10,7 @@ #include #ifdef PLL_CTL #include -# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) +# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS) #else #include # define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) @@ -55,7 +55,11 @@ static inline uint32_t early_get_uart_clk(void) if (!pll_is_bypassed()) { div = bfin_read_PLL_DIV(); ssel = (div & SSEL) >> SSEL_P; +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS + sclk = vco/ssel; +#else sclk = early_division(vco, ssel); +#endif } uclk = sclk; #ifdef CGU_DIV -- cgit v1.2.3 From 04eeb758e746d80848b4add1515493fe565a735e Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 14 Mar 2013 12:47:12 +0800 Subject: blackfin: Uart divisor should be set after their values are generated. Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/initcode.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 4b10b6c6b2..8ef0b92c23 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -715,8 +715,8 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) * for dividing which means we'd generate a libgcc reference. */ unsigned int sdivR, vcoR; - unsigned int dividend = sdivB * divB * vcoR; - unsigned int divisor = vcoB * sdivR; + unsigned int dividend; + unsigned int divisor; unsigned int quotient; serial_putc('a'); @@ -729,6 +729,9 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) sdivR = bfin_read_PLL_DIV() & 0xf; vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; #endif + + dividend = sdivB * divB * vcoR; + divisor = vcoB * sdivR; quotient = early_division(dividend, divisor); serial_early_put_div(quotient - ANOMALY_05000230); serial_putc('c'); -- cgit v1.2.3 From e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Sun, 7 Apr 2013 18:02:37 +0800 Subject: blackfin: Move blackfin watchdog driver out of the blackfin arch folder. - Enable hw_watchdog_init() in watchdog.h if CONFIG_HW_WATCHDOG is defined. - Move blackfin hw watchdog driver to the generic driver folder. - Call hw_watchdog_init() from blackfin board init code. - Reuse macro CONFIG_WATCHDOG_TIMEOUT_MSECS - Update README.watchdog accordingly Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/Makefile | 1 - arch/blackfin/cpu/initcode.c | 5 ++++- arch/blackfin/cpu/start.S | 26 ++++++++++++++++++-------- arch/blackfin/cpu/watchdog.c | 23 ----------------------- arch/blackfin/lib/board.c | 4 ++-- doc/README.watchdog | 3 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/bfin_wdt.c | 26 ++++++++++++++++++++++++++ include/configs/bfin_adi_common.h | 6 ++++++ include/watchdog.h | 3 +-- 10 files changed, 61 insertions(+), 37 deletions(-) delete mode 100644 arch/blackfin/cpu/watchdog.c create mode 100644 drivers/watchdog/bfin_wdt.c (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 0a72ec5df3..145f63eea7 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -25,7 +25,6 @@ COBJS-y += os_log.o COBJS-y += reset.o COBJS-y += serial.o COBJS-y += traps.o -COBJS-$(CONFIG_HW_WATCHDOG) += watchdog.o SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 8ef0b92c23..078209fc24 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -468,9 +469,11 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) bfin_write_SEC_GCTL(0x1); bfin_write_SEC_CCTL(0x1); #endif + bfin_write_WDOG_CTL(WDDIS); + SSYNC(); bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART - bfin_write_WDOG_CTL(0); + bfin_write_WDOG_CTL(WDEN); #endif serial_putc('f'); } diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 7155fc858b..1c6ae35275 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -65,20 +66,29 @@ ENTRY(_start) p5.h = HI(COREMMR_BASE); #ifdef CONFIG_HW_WATCHDOG -#ifndef __ADSPBF60x__ -# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START -# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000 -# endif - /* Program the watchdog with an initial timeout of ~5 seconds. + /* Program the watchdog with default timeout of ~5 seconds. * That should be long enough to bootstrap ourselves up and * then the common u-boot code can take over. */ + r1 = WDDIS; +# ifdef __ADSPBF60x__ + [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1; +# else + W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1; +# endif + SSYNC; r0 = 0; - r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START)); + r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS)); [p4 + (WDOG_CNT - SYSMMR_BASE)] = r0; + SSYNC; + r1 = WDEN; /* fire up the watchdog - R0.L above needs to be 0x0000 */ - W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0; -#endif +# ifdef __ADSPBF60x__ + [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1; +# else + W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1; +# endif + SSYNC; #endif /* Turn on the serial for debugging the init process */ diff --git a/arch/blackfin/cpu/watchdog.c b/arch/blackfin/cpu/watchdog.c deleted file mode 100644 index 1886bda0ae..0000000000 --- a/arch/blackfin/cpu/watchdog.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * watchdog.c - driver for Blackfin on-chip watchdog - * - * Copyright (c) 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void hw_watchdog_reset(void) -{ - bfin_write_WDOG_STAT(0); -} - -void hw_watchdog_init(void) -{ - bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */ - hw_watchdog_reset(); - bfin_write_WDOG_CTL(0x0); -} diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 85b859df72..f1d55470e8 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -279,9 +279,9 @@ void board_init_f(ulong bootflag) dcache_enable(); #endif -#ifdef CONFIG_WATCHDOG +#ifdef CONFIG_HW_WATCHDOG serial_early_puts("Setting up external watchdog\n"); - watchdog_init(); + hw_watchdog_init(); #endif #ifdef DEBUG diff --git a/doc/README.watchdog b/doc/README.watchdog index 33f31c2140..59f306b851 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -30,3 +30,6 @@ CONFIG_IMX_WATCHDOG CONFIG_XILINX_TB_WATCHDOG Available for Xilinx Axi platforms to service timebase watchdog timer. + +CONFIG_BFIN_WATCHDOG + Available for bf5xx and bf6xx to service the watchdog. diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 13e7c37686..d57578df6c 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -33,6 +33,7 @@ endif COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o COBJS-$(CONFIG_S5P) += s5p_wdt.o COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o +COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c new file mode 100644 index 0000000000..7a6756b2e5 --- /dev/null +++ b/drivers/watchdog/bfin_wdt.c @@ -0,0 +1,26 @@ +/* + * watchdog.c - driver for Blackfin on-chip watchdog + * + * Copyright (c) 2007-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include + +void hw_watchdog_reset(void) +{ + bfin_write_WDOG_STAT(0); +} + +void hw_watchdog_init(void) +{ + bfin_write_WDOG_CTL(WDDIS); + SSYNC(); + bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk()); + hw_watchdog_reset(); + bfin_write_WDOG_CTL(WDEN); +} diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index c986ba3d3e..0bcccf831b 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -314,5 +314,11 @@ #define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */ #define CONFIG_LZMA #define CONFIG_MONITOR_IS_IN_RAM +#ifdef CONFIG_HW_WATCHDOG +# define CONFIG_BFIN_WATCHDOG +# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000 +# endif +#endif #endif diff --git a/include/watchdog.h b/include/watchdog.h index 97ec186be3..d95e4b164d 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -108,8 +108,7 @@ int init_func_watchdog_reset(void); void reset_4xx_watchdog(void); #endif -/* Freescale i.MX */ -#if defined(CONFIG_IMX_WATCHDOG) && !defined(__ASSEMBLY__) +#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__) void hw_watchdog_init(void); #endif #endif /* _WATCHDOG_H_ */ -- cgit v1.2.3 From 9d803fc8125a3528f700da9064d1bfa3fbc56b13 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Sun, 7 Apr 2013 19:04:14 +0800 Subject: blackfin: Move blackfin serial driver out of blackfin arch folder. - Move blackfin serial driver to the generic driver folder. - Move blackfin serial headers to blackfin arch head folder. - Update the include path to blackfin serial header in start up code. Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/Makefile | 1 - arch/blackfin/cpu/cpu.c | 2 +- arch/blackfin/cpu/initcode.c | 5 +- arch/blackfin/cpu/serial.c | 412 ------------------------------------ arch/blackfin/cpu/serial.h | 131 ------------ arch/blackfin/cpu/serial1.h | 342 ------------------------------ arch/blackfin/cpu/serial4.h | 150 ------------- arch/blackfin/cpu/start.S | 3 +- arch/blackfin/include/asm/serial.h | 131 ++++++++++++ arch/blackfin/include/asm/serial1.h | 342 ++++++++++++++++++++++++++++++ arch/blackfin/include/asm/serial4.h | 150 +++++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_bfin.c | 411 +++++++++++++++++++++++++++++++++++ include/configs/bfin_adi_common.h | 3 + 14 files changed, 1042 insertions(+), 1042 deletions(-) delete mode 100644 arch/blackfin/cpu/serial.c delete mode 100644 arch/blackfin/cpu/serial.h delete mode 100644 arch/blackfin/cpu/serial1.h delete mode 100644 arch/blackfin/cpu/serial4.h create mode 100644 arch/blackfin/include/asm/serial.h create mode 100644 arch/blackfin/include/asm/serial1.h create mode 100644 arch/blackfin/include/asm/serial4.h create mode 100644 drivers/serial/serial_bfin.c (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 145f63eea7..929fc8b7ce 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -23,7 +23,6 @@ COBJS-y += interrupts.o COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o COBJS-y += os_log.o COBJS-y += reset.o -COBJS-y += serial.o COBJS-y += traps.o SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index d841f64c82..218f57ed38 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -16,9 +16,9 @@ #include #include #include +#include #include "cpu.h" -#include "serial.h" #include "initcode.h" ulong bfin_poweron_retx; diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 078209fc24..5fc06e11ff 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -16,10 +16,9 @@ #include #include #include +#include -#define BUG() while (1) { asm volatile("emuexcpt;"); } - -#include "serial.h" +#define BUG() while (1) asm volatile("emuexcpt;"); #ifndef __ADSPBF60x__ #include diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c deleted file mode 100644 index c453a03c0c..0000000000 --- a/arch/blackfin/cpu/serial.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * U-boot - serial.c Blackfin Serial Driver - * - * Copyright (c) 2005-2008 Analog Devices Inc. - * - * Copyright (c) 2003 Bas Vermeulen , - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on: - * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. - * Copyright(c) 2003 Metrowerks - * Copyright(c) 2001 Tony Z. Kou - * Copyright(c) 2001-2002 Arcturus Networks Inc. - * - * Based on code from 68328 version serial driver imlpementation which was: - * Copyright (C) 1995 David S. Miller - * Copyright (C) 1998 Kenneth Albanowski - * Copyright (C) 1998, 1999 D. Jeff Dionne - * Copyright (C) 1999 Vladimir Gurevich - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Licensed under the GPL-2 or later. - */ - -/* Anomaly notes: - * 05000086 - we don't support autobaud - * 05000099 - we only use DR bit, so losing others is not a problem - * 05000100 - we don't use the UART_IIR register - * 05000215 - we poll the uart (no dma/interrupts) - * 05000225 - no workaround possible, but this shouldnt cause errors ... - * 05000230 - we tweak the baud rate calculation slightly - * 05000231 - we always use 1 stop bit - * 05000309 - we always enable the uart before we modify it in anyway - * 05000350 - we always enable the uart regardless of boot mode - * 05000363 - we don't support break signals, so don't generate one - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_UART_CONSOLE - -#include "serial.h" - -#ifdef CONFIG_DEBUG_SERIAL -static uart_lsr_t cached_lsr[256]; -static uart_lsr_t cached_rbr[256]; -static size_t cache_count; - -/* The LSR is read-to-clear on some parts, so we have to make sure status - * bits aren't inadvertently lost when doing various tests. This also - * works around anomaly 05000099 at the same time by keeping a cumulative - * tally of all the status bits. - */ -static uart_lsr_t uart_lsr_save; -static uart_lsr_t uart_lsr_read(uint32_t uart_base) -{ - uart_lsr_t lsr = _lsr_read(pUART); - uart_lsr_save |= (lsr & (OE|PE|FE|BI)); - return lsr | uart_lsr_save; -} -/* Just do the clear for everyone since it can't hurt. */ -static void uart_lsr_clear(uint32_t uart_base) -{ - uart_lsr_save = 0; - _lsr_write(pUART, -1); -} -#else -/* When debugging is disabled, we only care about the DR bit, so if other - * bits get set/cleared, we don't really care since we don't read them - * anyways (and thus anomaly 05000099 is irrelevant). - */ -static inline uart_lsr_t uart_lsr_read(uint32_t uart_base) -{ - return _lsr_read(pUART); -} -static void uart_lsr_clear(uint32_t uart_base) -{ - _lsr_write(pUART, -1); -} -#endif - -static void uart_putc(uint32_t uart_base, const char c) -{ - /* send a \r for compatibility */ - if (c == '\n') - serial_putc('\r'); - - WATCHDOG_RESET(); - - /* wait for the hardware fifo to clear up */ - while (!(uart_lsr_read(uart_base) & THRE)) - continue; - - /* queue the character for transmission */ - bfin_write(&pUART->thr, c); - SSYNC(); - - WATCHDOG_RESET(); -} - -static int uart_tstc(uint32_t uart_base) -{ - WATCHDOG_RESET(); - return (uart_lsr_read(uart_base) & DR) ? 1 : 0; -} - -static int uart_getc(uint32_t uart_base) -{ - uint16_t uart_rbr_val; - - /* wait for data ! */ - while (!uart_tstc(uart_base)) - continue; - - /* grab the new byte */ - uart_rbr_val = bfin_read(&pUART->rbr); - -#ifdef CONFIG_DEBUG_SERIAL - /* grab & clear the LSR */ - uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base); - - cached_lsr[cache_count] = uart_lsr_val; - cached_rbr[cache_count] = uart_rbr_val; - cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr); - - if (uart_lsr_val & (OE|PE|FE|BI)) { - printf("\n[SERIAL ERROR]\n"); - do { - --cache_count; - printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count, - cached_rbr[cache_count], cached_lsr[cache_count]); - } while (cache_count > 0); - return -1; - } -#endif - uart_lsr_clear(uart_base); - - return uart_rbr_val; -} - -#if CONFIG_POST & CONFIG_SYS_POST_UART -# define LOOP(x) x -#else -# define LOOP(x) -#endif - -#if BFIN_UART_HW_VER < 4 - -LOOP( -static void uart_loop(uint32_t uart_base, int state) -{ - u16 mcr; - - /* Drain the TX fifo first so bytes don't come back */ - while (!(uart_lsr_read(uart_base) & TEMT)) - continue; - - mcr = bfin_read(&pUART->mcr); - if (state) - mcr |= LOOP_ENA | MRTS; - else - mcr &= ~(LOOP_ENA | MRTS); - bfin_write(&pUART->mcr, mcr); -} -) - -#else - -LOOP( -static void uart_loop(uint32_t uart_base, int state) -{ - u32 control; - - /* Drain the TX fifo first so bytes don't come back */ - while (!(uart_lsr_read(uart_base) & TEMT)) - continue; - - control = bfin_read(&pUART->control); - if (state) - control |= LOOP_ENA | MRTS; - else - control &= ~(LOOP_ENA | MRTS); - bfin_write(&pUART->control, control); -} -) - -#endif - -static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud) -{ -#ifdef CONFIG_DEBUG_EARLY_SERIAL - serial_early_set_baud(uart_base, baud); -#else - uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16) - - ANOMALY_05000230; - - /* Program the divisor to get the baud rate we want */ - serial_set_divisor(uart_base, divisor); -#endif -} - -static void uart_puts(uint32_t uart_base, const char *s) -{ - while (*s) - uart_putc(uart_base, *s++); -} - -#define DECL_BFIN_UART(n) \ -static int uart##n##_init(void) \ -{ \ - const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \ - peripheral_request_list(pins, "bfin-uart"); \ - uart_init(MMR_UART(n)); \ - __serial_set_baud(MMR_UART(n), gd->baudrate); \ - uart_lsr_clear(MMR_UART(n)); \ - return 0; \ -} \ -\ -static int uart##n##_uninit(void) \ -{ \ - return serial_early_uninit(MMR_UART(n)); \ -} \ -\ -static void uart##n##_setbrg(void) \ -{ \ - __serial_set_baud(MMR_UART(n), gd->baudrate); \ -} \ -\ -static int uart##n##_getc(void) \ -{ \ - return uart_getc(MMR_UART(n)); \ -} \ -\ -static int uart##n##_tstc(void) \ -{ \ - return uart_tstc(MMR_UART(n)); \ -} \ -\ -static void uart##n##_putc(const char c) \ -{ \ - uart_putc(MMR_UART(n), c); \ -} \ -\ -static void uart##n##_puts(const char *s) \ -{ \ - uart_puts(MMR_UART(n), s); \ -} \ -\ -LOOP( \ -static void uart##n##_loop(int state) \ -{ \ - uart_loop(MMR_UART(n), state); \ -} \ -) \ -\ -struct serial_device bfin_serial##n##_device = { \ - .name = "bfin_uart"#n, \ - .start = uart##n##_init, \ - .stop = uart##n##_uninit, \ - .setbrg = uart##n##_setbrg, \ - .getc = uart##n##_getc, \ - .tstc = uart##n##_tstc, \ - .putc = uart##n##_putc, \ - .puts = uart##n##_puts, \ - LOOP(.loop = uart##n##_loop) \ -}; - -#ifdef UART0_RBR -DECL_BFIN_UART(0) -#endif -#ifdef UART1_RBR -DECL_BFIN_UART(1) -#endif -#ifdef UART2_RBR -DECL_BFIN_UART(2) -#endif -#ifdef UART3_RBR -DECL_BFIN_UART(3) -#endif - -__weak struct serial_device *default_serial_console(void) -{ -#if CONFIG_UART_CONSOLE == 0 - return &bfin_serial0_device; -#elif CONFIG_UART_CONSOLE == 1 - return &bfin_serial1_device; -#elif CONFIG_UART_CONSOLE == 2 - return &bfin_serial2_device; -#elif CONFIG_UART_CONSOLE == 3 - return &bfin_serial3_device; -#endif -} - -void bfin_serial_initialize(void) -{ -#ifdef UART0_RBR - serial_register(&bfin_serial0_device); -#endif -#ifdef UART1_RBR - serial_register(&bfin_serial1_device); -#endif -#ifdef UART2_RBR - serial_register(&bfin_serial2_device); -#endif -#ifdef UART3_RBR - serial_register(&bfin_serial3_device); -#endif -} - -#ifdef CONFIG_DEBUG_EARLY_SERIAL -inline void uart_early_putc(uint32_t uart_base, const char c) -{ - /* send a \r for compatibility */ - if (c == '\n') - uart_early_putc(uart_base, '\r'); - - /* wait for the hardware fifo to clear up */ - while (!(_lsr_read(pUART) & THRE)) - continue; - - /* queue the character for transmission */ - bfin_write(&pUART->thr, c); - SSYNC(); -} - -void uart_early_puts(const char *s) -{ - while (*s) - uart_early_putc(UART_BASE, *s++); -} - -/* Symbol for our assembly to call. */ -void _serial_early_set_baud(uint32_t baud) -{ - serial_early_set_baud(UART_BASE, baud); -} - -/* Symbol for our assembly to call. */ -void _serial_early_init(void) -{ - serial_early_init(UART_BASE); -} -#endif - -#elif defined(CONFIG_UART_MEM) - -char serial_logbuf[CONFIG_UART_MEM]; -char *serial_logbuf_head = serial_logbuf; - -int serial_mem_init(void) -{ - serial_logbuf_head = serial_logbuf; - return 0; -} - -void serial_mem_setbrg(void) -{ -} - -int serial_mem_tstc(void) -{ - return 0; -} - -int serial_mem_getc(void) -{ - return 0; -} - -void serial_mem_putc(const char c) -{ - *serial_logbuf_head = c; - if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM) - serial_logbuf_head = serial_logbuf; -} - -void serial_mem_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - -struct serial_device bfin_serial_mem_device = { - .name = "bfin_uart_mem", - .start = serial_mem_init, - .setbrg = serial_mem_setbrg, - .getc = serial_mem_getc, - .tstc = serial_mem_tstc, - .putc = serial_mem_putc, - .puts = serial_mem_puts, -}; - - -__weak struct serial_device *default_serial_console(void) -{ - return &bfin_serial_mem_device; -} - -void bfin_serial_initialize(void) -{ - serial_register(&bfin_serial_mem_device); -} -#endif /* CONFIG_UART_MEM */ diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h deleted file mode 100644 index 87a337d1b4..0000000000 --- a/arch/blackfin/cpu/serial.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * serial.h - common serial defines for early debug and serial driver. - * any functions defined here must be always_inline since - * initcode cannot have function calls. - * - * Copyright (c) 2004-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_CPU_SERIAL_H__ -#define __BFIN_CPU_SERIAL_H__ - -#include -#include - -#ifndef CONFIG_UART_CONSOLE -# define CONFIG_UART_CONSOLE 0 -#endif - -#ifdef CONFIG_DEBUG_EARLY_SERIAL -# define BFIN_DEBUG_EARLY_SERIAL 1 -#else -# define BFIN_DEBUG_EARLY_SERIAL 0 -#endif - -#if defined(__ADSPBF60x__) -# define BFIN_UART_HW_VER 4 -#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__) -# define BFIN_UART_HW_VER 2 -#else -# define BFIN_UART_HW_VER 1 -#endif - -#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx -#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) -#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) -#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) - -#define pUART ((volatile struct bfin_mmr_serial *)uart_base) - -#ifndef __ASSEMBLY__ -__attribute__((always_inline)) -static inline void serial_do_portmux(void); -#endif - -#if BFIN_UART_HW_VER < 4 -# include "serial1.h" -#else -# include "serial4.h" -#endif - -#ifndef __ASSEMBLY__ - -__attribute__((always_inline)) -static inline void serial_do_portmux(void) -{ - if (!BFIN_DEBUG_EARLY_SERIAL) { - const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, }; - peripheral_request_list(pins, "bfin-uart"); - return; - } - - serial_early_do_portmux(); -} - -#ifndef BFIN_IN_INITCODE -__attribute__((always_inline)) -static inline void serial_early_puts(const char *s) -{ - if (BFIN_DEBUG_EARLY_SERIAL) { - serial_puts("Early: "); - serial_puts(s); - } -} -#endif - -#else - -.macro serial_early_init -#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) - call __serial_early_init; -#endif -.endm - -.macro serial_early_set_baud -#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) - R0.L = LO(CONFIG_BAUDRATE); - R0.H = HI(CONFIG_BAUDRATE); - call __serial_early_set_baud; -#endif -.endm - -#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS -#define update_serial_early_string_addr \ - R1.L = _start; \ - R1.H = _start; \ - R0 = R0 - R1; \ - R1.L = 0; \ - R1.H = 0x2000; \ - R0 = R0 + R1; -#else -#define update_serial_early_string_addr -#endif - -/* Since we embed the string right into our .text section, we need - * to find its address. We do this by getting our PC and adding 2 - * bytes (which is the length of the jump instruction). Then we - * pass this address to serial_puts(). - */ -#ifdef CONFIG_DEBUG_EARLY_SERIAL -# define serial_early_puts(str) \ - .section .rodata; \ - 7: \ - .ascii "Early:"; \ - .ascii __FILE__; \ - .ascii ": "; \ - .ascii str; \ - .asciz "\n"; \ - .previous; \ - R0.L = 7b; \ - R0.H = 7b; \ - update_serial_early_string_addr \ - call _uart_early_puts; -#else -# define serial_early_puts(str) -#endif - -#endif - -#endif diff --git a/arch/blackfin/cpu/serial1.h b/arch/blackfin/cpu/serial1.h deleted file mode 100644 index 467d3817f1..0000000000 --- a/arch/blackfin/cpu/serial1.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * serial.h - common serial defines for early debug and serial driver. - * any functions defined here must be always_inline since - * initcode cannot have function calls. - * - * Copyright (c) 2004-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_CPU_SERIAL1_H__ -#define __BFIN_CPU_SERIAL1_H__ - -#include - -#ifndef __ASSEMBLY__ - -#include - -#define MMR_UART(n) _PASTE_UART(n, UART, DLL) -#ifdef UART_DLL -# define UART0_DLL UART_DLL -# if CONFIG_UART_CONSOLE != 0 -# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART -# endif -#endif -#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) - -#define LOB(x) ((x) & 0xFF) -#define HIB(x) (((x) >> 8) & 0xFF) - -/* - * All Blackfin system MMRs are padded to 32bits even if the register - * itself is only 16bits. So use a helper macro to streamline this. - */ -struct bfin_mmr_serial { -#if BFIN_UART_HW_VER == 2 - u16 dll; - u16 __pad_0; - u16 dlh; - u16 __pad_1; - u16 gctl; - u16 __pad_2; - u16 lcr; - u16 __pad_3; - u16 mcr; - u16 __pad_4; - u16 lsr; - u16 __pad_5; - u16 msr; - u16 __pad_6; - u16 scr; - u16 __pad_7; - u16 ier_set; - u16 __pad_8; - u16 ier_clear; - u16 __pad_9; - u16 thr; - u16 __pad_10; - u16 rbr; - u16 __pad_11; -#else - union { - u16 dll; - u16 thr; - const u16 rbr; - }; - const u16 __spad0; - union { - u16 dlh; - u16 ier; - }; - const u16 __spad1; - const u16 iir; - u16 __pad_0; - u16 lcr; - u16 __pad_1; - u16 mcr; - u16 __pad_2; - u16 lsr; - u16 __pad_3; - u16 msr; - u16 __pad_4; - u16 scr; - u16 __pad_5; - const u32 __spad2; - u16 gctl; - u16 __pad_6; -#endif -}; - -#define uart_lsr_t uint32_t -#define _lsr_read(p) bfin_read(&p->lsr) -#define _lsr_write(p, v) bfin_write(&p->lsr, v) - -#if BFIN_UART_HW_VER == 2 -# define ACCESS_LATCH() -# define ACCESS_PORT_IER() -#else -# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB) -# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB) -#endif - -__attribute__((always_inline)) -static inline void serial_early_do_mach_portmux(char port, int mux_mask, - int mux_func, int port_pin) -{ - switch (port) { -#if defined(__ADSPBF54x__) - case 'B': - bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin); - break; - case 'E': - bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin); - break; -#endif -#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__) - case 'F': - bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin); - break; - case 'G': - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin); - break; - case 'H': - bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin); - break; -#endif - default: - break; - } -} - -__attribute__((always_inline)) -static inline void serial_early_do_portmux(void) -{ -#if defined(__ADSPBF50x__) - switch (CONFIG_UART_CONSOLE) { - case 0: - serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, - PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */ - serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, - PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */ - break; - case 1: - serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, - PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */ - serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, - PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */ - break; - } -#elif defined(__ADSPBF51x__) - switch (CONFIG_UART_CONSOLE) { - case 0: - serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, - PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */ - serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, - PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */ - break; - case 1: - serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, - PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */ - serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, - PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */ - break; - } -#elif defined(__ADSPBF52x__) - switch (CONFIG_UART_CONSOLE) { - case 0: - serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, - PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */ - serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, - PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */ - break; - case 1: - serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, - PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */ - serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, - PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */ - break; - } -#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) - const uint16_t func[] = { PFDE, PFTE, }; - bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); - bfin_write_PORTF_FER(bfin_read_PORTF_FER() | - (1 << P_IDENT(P_UART(RX))) | - (1 << P_IDENT(P_UART(TX)))); -#elif defined(__ADSPBF54x__) - switch (CONFIG_UART_CONSOLE) { - case 0: - serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK, - PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */ - serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK, - PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */ - break; - case 1: - serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK, - PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */ - serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK, - PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */ - break; - case 2: - serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK, - PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */ - serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK, - PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */ - break; - case 3: - serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK, - PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */ - serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK, - PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */ - break; - } -#elif defined(__ADSPBF561__) - /* UART pins could be GPIO, but they aren't pin muxed. */ -#else -# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) -# error "missing portmux logic for UART" -# endif -#endif - SSYNC(); -} - -__attribute__((always_inline)) -static inline int uart_init(uint32_t uart_base) -{ - /* always enable UART -- avoids anomalies 05000309 and 05000350 */ - bfin_write(&pUART->gctl, UCEN); - - /* Set LCR to Word Lengh 8-bit word select */ - bfin_write(&pUART->lcr, WLS_8); - - SSYNC(); - - return 0; -} - -__attribute__((always_inline)) -static inline int serial_early_init(uint32_t uart_base) -{ - /* handle portmux crap on different Blackfins */ - serial_do_portmux(); - - return uart_init(uart_base); -} - -__attribute__((always_inline)) -static inline int serial_early_uninit(uint32_t uart_base) -{ - /* disable the UART by clearing UCEN */ - bfin_write(&pUART->gctl, 0); - - return 0; -} - -__attribute__((always_inline)) -static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) -{ - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - /* Program the divisor to get the baud rate we want */ - bfin_write(&pUART->dll, LOB(divisor)); - bfin_write(&pUART->dlh, HIB(divisor)); - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); -} - -__attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) -{ - /* Translate from baud into divisor in terms of SCLK. The - * weird multiplication is to make sure we over sample just - * a little rather than under sample the incoming signals. - */ -#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS - uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16) - - ANOMALY_05000230; -#else - uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8), - baud * 16) - ANOMALY_05000230; -#endif - - serial_set_divisor(uart_base, divisor); -} - -__attribute__((always_inline)) -static inline void serial_early_put_div(uint16_t divisor) -{ - uint32_t uart_base = UART_BASE; - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - /* Program the divisor to get the baud rate we want */ - bfin_write(&pUART->dll, LOB(divisor)); - bfin_write(&pUART->dlh, HIB(divisor)); - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); -} - -__attribute__((always_inline)) -static inline uint16_t serial_early_get_div(void) -{ - uint32_t uart_base = UART_BASE; - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - uint8_t dll = bfin_read(&pUART->dll); - uint8_t dlh = bfin_read(&pUART->dlh); - uint16_t divisor = (dlh << 8) | dll; - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); - - return divisor; -} - -#endif - -#endif diff --git a/arch/blackfin/cpu/serial4.h b/arch/blackfin/cpu/serial4.h deleted file mode 100644 index 65483960b9..0000000000 --- a/arch/blackfin/cpu/serial4.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * serial.h - common serial defines for early debug and serial driver. - * any functions defined here must be always_inline since - * initcode cannot have function calls. - * - * Copyright (c) 2004-2011 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_CPU_SERIAL4_H__ -#define __BFIN_CPU_SERIAL4_H__ - -#include - -#ifndef __ASSEMBLY__ - -#include - -#define MMR_UART(n) _PASTE_UART(n, UART, REVID) -#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) - -struct bfin_mmr_serial { - u32 revid; - u32 control; - u32 status; - u32 scr; - u32 clock; - u32 emask; - u32 emaskst; - u32 emaskcl; - u32 rbr; - u32 thr; - u32 taip; - u32 tsr; - u32 rsr; - u32 txdiv_cnt; - u32 rxdiv_cnt; -}; -#define uart_lsr_t uint32_t -#define _lsr_read(p) bfin_read(&p->status) -#define _lsr_write(p, v) bfin_write(&p->status, v) - -__attribute__((always_inline)) -static inline void serial_early_do_mach_portmux(char port, int mux_mask, - int mux_func, int port_pin) -{ - switch (port) { - case 'D': - bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTD_FER_SET(port_pin); - break; - case 'G': - bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & - ~mux_mask) | mux_func); - bfin_write_PORTG_FER_SET(port_pin); - break; - } -} - -__attribute__((always_inline)) -static inline void serial_early_do_portmux(void) -{ -#if defined(__ADSPBF60x__) - switch (CONFIG_UART_CONSOLE) { - case 0: - serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, - PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ - serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, - PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ - break; - case 1: - serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, - PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ - serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, - PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ - break; - } -#else -# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) -# error "missing portmux logic for UART" -# endif -#endif - SSYNC(); -} - -__attribute__((always_inline)) -static inline int uart_init(uint32_t uart_base) -{ - /* always enable UART to 8-bit mode */ - bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); - - SSYNC(); - - return 0; -} - -__attribute__((always_inline)) -static inline int serial_early_init(uint32_t uart_base) -{ - /* handle portmux crap on different Blackfins */ - serial_do_portmux(); - - return uart_init(uart_base); -} - -__attribute__((always_inline)) -static inline int serial_early_uninit(uint32_t uart_base) -{ - /* disable the UART by clearing UEN */ - bfin_write(&pUART->control, 0); - - return 0; -} - -__attribute__((always_inline)) -static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) -{ - /* Program the divisor to get the baud rate we want */ - bfin_write(&pUART->clock, divisor); - SSYNC(); -} - -__attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) -{ - uint16_t divisor = early_division(early_get_uart_clk(), baud * 16); - - /* Program the divisor to get the baud rate we want */ - serial_set_divisor(uart_base, divisor); -} - -__attribute__((always_inline)) -static inline void serial_early_put_div(uint32_t divisor) -{ - uint32_t uart_base = UART_BASE; - bfin_write(&pUART->clock, divisor); -} - -__attribute__((always_inline)) -static inline uint32_t serial_early_get_div(void) -{ - uint32_t uart_base = UART_BASE; - return bfin_read(&pUART->clock); -} - -#endif - -#endif diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 1c6ae35275..da084a87c6 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -35,8 +35,7 @@ #include #include #include - -#include "serial.h" +#include /* It may seem odd that we make calls to functions even though we haven't * relocated ourselves yet out of {flash,ram,wherever}. This is OK because diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h new file mode 100644 index 0000000000..87a337d1b4 --- /dev/null +++ b/arch/blackfin/include/asm/serial.h @@ -0,0 +1,131 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL_H__ +#define __BFIN_CPU_SERIAL_H__ + +#include +#include + +#ifndef CONFIG_UART_CONSOLE +# define CONFIG_UART_CONSOLE 0 +#endif + +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define BFIN_DEBUG_EARLY_SERIAL 1 +#else +# define BFIN_DEBUG_EARLY_SERIAL 0 +#endif + +#if defined(__ADSPBF60x__) +# define BFIN_UART_HW_VER 4 +#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__) +# define BFIN_UART_HW_VER 2 +#else +# define BFIN_UART_HW_VER 1 +#endif + +#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx +#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) +#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) +#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) + +#define pUART ((volatile struct bfin_mmr_serial *)uart_base) + +#ifndef __ASSEMBLY__ +__attribute__((always_inline)) +static inline void serial_do_portmux(void); +#endif + +#if BFIN_UART_HW_VER < 4 +# include "serial1.h" +#else +# include "serial4.h" +#endif + +#ifndef __ASSEMBLY__ + +__attribute__((always_inline)) +static inline void serial_do_portmux(void) +{ + if (!BFIN_DEBUG_EARLY_SERIAL) { + const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, }; + peripheral_request_list(pins, "bfin-uart"); + return; + } + + serial_early_do_portmux(); +} + +#ifndef BFIN_IN_INITCODE +__attribute__((always_inline)) +static inline void serial_early_puts(const char *s) +{ + if (BFIN_DEBUG_EARLY_SERIAL) { + serial_puts("Early: "); + serial_puts(s); + } +} +#endif + +#else + +.macro serial_early_init +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) + call __serial_early_init; +#endif +.endm + +.macro serial_early_set_baud +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) + R0.L = LO(CONFIG_BAUDRATE); + R0.H = HI(CONFIG_BAUDRATE); + call __serial_early_set_baud; +#endif +.endm + +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS +#define update_serial_early_string_addr \ + R1.L = _start; \ + R1.H = _start; \ + R0 = R0 - R1; \ + R1.L = 0; \ + R1.H = 0x2000; \ + R0 = R0 + R1; +#else +#define update_serial_early_string_addr +#endif + +/* Since we embed the string right into our .text section, we need + * to find its address. We do this by getting our PC and adding 2 + * bytes (which is the length of the jump instruction). Then we + * pass this address to serial_puts(). + */ +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define serial_early_puts(str) \ + .section .rodata; \ + 7: \ + .ascii "Early:"; \ + .ascii __FILE__; \ + .ascii ": "; \ + .ascii str; \ + .asciz "\n"; \ + .previous; \ + R0.L = 7b; \ + R0.H = 7b; \ + update_serial_early_string_addr \ + call _uart_early_puts; +#else +# define serial_early_puts(str) +#endif + +#endif + +#endif diff --git a/arch/blackfin/include/asm/serial1.h b/arch/blackfin/include/asm/serial1.h new file mode 100644 index 0000000000..467d3817f1 --- /dev/null +++ b/arch/blackfin/include/asm/serial1.h @@ -0,0 +1,342 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL1_H__ +#define __BFIN_CPU_SERIAL1_H__ + +#include + +#ifndef __ASSEMBLY__ + +#include + +#define MMR_UART(n) _PASTE_UART(n, UART, DLL) +#ifdef UART_DLL +# define UART0_DLL UART_DLL +# if CONFIG_UART_CONSOLE != 0 +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART +# endif +#endif +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +#define LOB(x) ((x) & 0xFF) +#define HIB(x) (((x) >> 8) & 0xFF) + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +struct bfin_mmr_serial { +#if BFIN_UART_HW_VER == 2 + u16 dll; + u16 __pad_0; + u16 dlh; + u16 __pad_1; + u16 gctl; + u16 __pad_2; + u16 lcr; + u16 __pad_3; + u16 mcr; + u16 __pad_4; + u16 lsr; + u16 __pad_5; + u16 msr; + u16 __pad_6; + u16 scr; + u16 __pad_7; + u16 ier_set; + u16 __pad_8; + u16 ier_clear; + u16 __pad_9; + u16 thr; + u16 __pad_10; + u16 rbr; + u16 __pad_11; +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __spad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __spad1; + const u16 iir; + u16 __pad_0; + u16 lcr; + u16 __pad_1; + u16 mcr; + u16 __pad_2; + u16 lsr; + u16 __pad_3; + u16 msr; + u16 __pad_4; + u16 scr; + u16 __pad_5; + const u32 __spad2; + u16 gctl; + u16 __pad_6; +#endif +}; + +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->lsr) +#define _lsr_write(p, v) bfin_write(&p->lsr, v) + +#if BFIN_UART_HW_VER == 2 +# define ACCESS_LATCH() +# define ACCESS_PORT_IER() +#else +# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB) +# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB) +#endif + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { +#if defined(__ADSPBF54x__) + case 'B': + bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin); + break; + case 'E': + bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin); + break; +#endif +#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__) + case 'F': + bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin); + break; + case 'H': + bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin); + break; +#endif + default: + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF50x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */ + break; + } +#elif defined(__ADSPBF51x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */ + break; + } +#elif defined(__ADSPBF52x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */ + break; + } +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) + const uint16_t func[] = { PFDE, PFTE, }; + bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | + (1 << P_IDENT(P_UART(RX))) | + (1 << P_IDENT(P_UART(TX)))); +#elif defined(__ADSPBF54x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */ + serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK, + PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK, + PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */ + break; + case 2: + serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK, + PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */ + break; + case 3: + serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK, + PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */ + break; + } +#elif defined(__ADSPBF561__) + /* UART pins could be GPIO, but they aren't pin muxed. */ +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART -- avoids anomalies 05000309 and 05000350 */ + bfin_write(&pUART->gctl, UCEN); + + /* Set LCR to Word Lengh 8-bit word select */ + bfin_write(&pUART->lcr, WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UCEN */ + bfin_write(&pUART->gctl, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) +{ + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + /* Translate from baud into divisor in terms of SCLK. The + * weird multiplication is to make sure we over sample just + * a little rather than under sample the incoming signals. + */ +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS + uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16) + - ANOMALY_05000230; +#else + uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8), + baud * 16) - ANOMALY_05000230; +#endif + + serial_set_divisor(uart_base, divisor); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint16_t divisor) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint16_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + uint8_t dll = bfin_read(&pUART->dll); + uint8_t dlh = bfin_read(&pUART->dlh); + uint16_t divisor = (dlh << 8) | dll; + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); + + return divisor; +} + +#endif + +#endif diff --git a/arch/blackfin/include/asm/serial4.h b/arch/blackfin/include/asm/serial4.h new file mode 100644 index 0000000000..65483960b9 --- /dev/null +++ b/arch/blackfin/include/asm/serial4.h @@ -0,0 +1,150 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL4_H__ +#define __BFIN_CPU_SERIAL4_H__ + +#include + +#ifndef __ASSEMBLY__ + +#include + +#define MMR_UART(n) _PASTE_UART(n, UART, REVID) +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +struct bfin_mmr_serial { + u32 revid; + u32 control; + u32 status; + u32 scr; + u32 clock; + u32 emask; + u32 emaskst; + u32 emaskcl; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv_cnt; + u32 rxdiv_cnt; +}; +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->status) +#define _lsr_write(p, v) bfin_write(&p->status, v) + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { + case 'D': + bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTD_FER_SET(port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER_SET(port_pin); + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF60x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ + serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ + break; + case 1: + serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, + PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, + PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ + break; + } +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART to 8-bit mode */ + bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UEN */ + bfin_write(&pUART->control, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) +{ + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->clock, divisor); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + uint16_t divisor = early_division(early_get_uart_clk(), baud * 16); + + /* Program the divisor to get the baud rate we want */ + serial_set_divisor(uart_base, divisor); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint32_t divisor) +{ + uint32_t uart_base = UART_BASE; + bfin_write(&pUART->clock, divisor); +} + +__attribute__((always_inline)) +static inline uint32_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + return bfin_read(&pUART->clock); +} + +#endif + +#endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index fbc4e97e98..442b7ea0df 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o +COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_bfin.c b/drivers/serial/serial_bfin.c new file mode 100644 index 0000000000..0443b8427a --- /dev/null +++ b/drivers/serial/serial_bfin.c @@ -0,0 +1,411 @@ +/* + * U-boot - serial.c Blackfin Serial Driver + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Copyright (c) 2003 Bas Vermeulen , + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on: + * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. + * Copyright(c) 2003 Metrowerks + * Copyright(c) 2001 Tony Z. Kou + * Copyright(c) 2001-2002 Arcturus Networks Inc. + * + * Based on code from 68328 version serial driver imlpementation which was: + * Copyright (C) 1995 David S. Miller + * Copyright (C) 1998 Kenneth Albanowski + * Copyright (C) 1998, 1999 D. Jeff Dionne + * Copyright (C) 1999 Vladimir Gurevich + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +/* Anomaly notes: + * 05000086 - we don't support autobaud + * 05000099 - we only use DR bit, so losing others is not a problem + * 05000100 - we don't use the UART_IIR register + * 05000215 - we poll the uart (no dma/interrupts) + * 05000225 - no workaround possible, but this shouldnt cause errors ... + * 05000230 - we tweak the baud rate calculation slightly + * 05000231 - we always use 1 stop bit + * 05000309 - we always enable the uart before we modify it in anyway + * 05000350 - we always enable the uart regardless of boot mode + * 05000363 - we don't support break signals, so don't generate one + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_UART_CONSOLE + +#ifdef CONFIG_DEBUG_SERIAL +static uart_lsr_t cached_lsr[256]; +static uart_lsr_t cached_rbr[256]; +static size_t cache_count; + +/* The LSR is read-to-clear on some parts, so we have to make sure status + * bits aren't inadvertently lost when doing various tests. This also + * works around anomaly 05000099 at the same time by keeping a cumulative + * tally of all the status bits. + */ +static uart_lsr_t uart_lsr_save; +static uart_lsr_t uart_lsr_read(uint32_t uart_base) +{ + uart_lsr_t lsr = _lsr_read(pUART); + uart_lsr_save |= (lsr & (OE|PE|FE|BI)); + return lsr | uart_lsr_save; +} +/* Just do the clear for everyone since it can't hurt. */ +static void uart_lsr_clear(uint32_t uart_base) +{ + uart_lsr_save = 0; + _lsr_write(pUART, -1); +} +#else +/* When debugging is disabled, we only care about the DR bit, so if other + * bits get set/cleared, we don't really care since we don't read them + * anyways (and thus anomaly 05000099 is irrelevant). + */ +static inline uart_lsr_t uart_lsr_read(uint32_t uart_base) +{ + return _lsr_read(pUART); +} +static void uart_lsr_clear(uint32_t uart_base) +{ + _lsr_write(pUART, -1); +} +#endif + +static void uart_putc(uint32_t uart_base, const char c) +{ + /* send a \r for compatibility */ + if (c == '\n') + serial_putc('\r'); + + WATCHDOG_RESET(); + + /* wait for the hardware fifo to clear up */ + while (!(uart_lsr_read(uart_base) & THRE)) + continue; + + /* queue the character for transmission */ + bfin_write(&pUART->thr, c); + SSYNC(); + + WATCHDOG_RESET(); +} + +static int uart_tstc(uint32_t uart_base) +{ + WATCHDOG_RESET(); + return (uart_lsr_read(uart_base) & DR) ? 1 : 0; +} + +static int uart_getc(uint32_t uart_base) +{ + uint16_t uart_rbr_val; + + /* wait for data ! */ + while (!uart_tstc(uart_base)) + continue; + + /* grab the new byte */ + uart_rbr_val = bfin_read(&pUART->rbr); + +#ifdef CONFIG_DEBUG_SERIAL + /* grab & clear the LSR */ + uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base); + + cached_lsr[cache_count] = uart_lsr_val; + cached_rbr[cache_count] = uart_rbr_val; + cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr); + + if (uart_lsr_val & (OE|PE|FE|BI)) { + printf("\n[SERIAL ERROR]\n"); + do { + --cache_count; + printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count, + cached_rbr[cache_count], cached_lsr[cache_count]); + } while (cache_count > 0); + return -1; + } +#endif + uart_lsr_clear(uart_base); + + return uart_rbr_val; +} + +#if CONFIG_POST & CONFIG_SYS_POST_UART +# define LOOP(x) x +#else +# define LOOP(x) +#endif + +#if BFIN_UART_HW_VER < 4 + +LOOP( +static void uart_loop(uint32_t uart_base, int state) +{ + u16 mcr; + + /* Drain the TX fifo first so bytes don't come back */ + while (!(uart_lsr_read(uart_base) & TEMT)) + continue; + + mcr = bfin_read(&pUART->mcr); + if (state) + mcr |= LOOP_ENA | MRTS; + else + mcr &= ~(LOOP_ENA | MRTS); + bfin_write(&pUART->mcr, mcr); +} +) + +#else + +LOOP( +static void uart_loop(uint32_t uart_base, int state) +{ + u32 control; + + /* Drain the TX fifo first so bytes don't come back */ + while (!(uart_lsr_read(uart_base) & TEMT)) + continue; + + control = bfin_read(&pUART->control); + if (state) + control |= LOOP_ENA | MRTS; + else + control &= ~(LOOP_ENA | MRTS); + bfin_write(&pUART->control, control); +} +) + +#endif + +static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud) +{ +#ifdef CONFIG_DEBUG_EARLY_SERIAL + serial_early_set_baud(uart_base, baud); +#else + uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16) + - ANOMALY_05000230; + + /* Program the divisor to get the baud rate we want */ + serial_set_divisor(uart_base, divisor); +#endif +} + +static void uart_puts(uint32_t uart_base, const char *s) +{ + while (*s) + uart_putc(uart_base, *s++); +} + +#define DECL_BFIN_UART(n) \ +static int uart##n##_init(void) \ +{ \ + const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \ + peripheral_request_list(pins, "bfin-uart"); \ + uart_init(MMR_UART(n)); \ + __serial_set_baud(MMR_UART(n), gd->baudrate); \ + uart_lsr_clear(MMR_UART(n)); \ + return 0; \ +} \ +\ +static int uart##n##_uninit(void) \ +{ \ + return serial_early_uninit(MMR_UART(n)); \ +} \ +\ +static void uart##n##_setbrg(void) \ +{ \ + __serial_set_baud(MMR_UART(n), gd->baudrate); \ +} \ +\ +static int uart##n##_getc(void) \ +{ \ + return uart_getc(MMR_UART(n)); \ +} \ +\ +static int uart##n##_tstc(void) \ +{ \ + return uart_tstc(MMR_UART(n)); \ +} \ +\ +static void uart##n##_putc(const char c) \ +{ \ + uart_putc(MMR_UART(n), c); \ +} \ +\ +static void uart##n##_puts(const char *s) \ +{ \ + uart_puts(MMR_UART(n), s); \ +} \ +\ +LOOP( \ +static void uart##n##_loop(int state) \ +{ \ + uart_loop(MMR_UART(n), state); \ +} \ +) \ +\ +struct serial_device bfin_serial##n##_device = { \ + .name = "bfin_uart"#n, \ + .start = uart##n##_init, \ + .stop = uart##n##_uninit, \ + .setbrg = uart##n##_setbrg, \ + .getc = uart##n##_getc, \ + .tstc = uart##n##_tstc, \ + .putc = uart##n##_putc, \ + .puts = uart##n##_puts, \ + LOOP(.loop = uart##n##_loop) \ +}; + +#ifdef UART0_RBR +DECL_BFIN_UART(0) +#endif +#ifdef UART1_RBR +DECL_BFIN_UART(1) +#endif +#ifdef UART2_RBR +DECL_BFIN_UART(2) +#endif +#ifdef UART3_RBR +DECL_BFIN_UART(3) +#endif + +__weak struct serial_device *default_serial_console(void) +{ +#if CONFIG_UART_CONSOLE == 0 + return &bfin_serial0_device; +#elif CONFIG_UART_CONSOLE == 1 + return &bfin_serial1_device; +#elif CONFIG_UART_CONSOLE == 2 + return &bfin_serial2_device; +#elif CONFIG_UART_CONSOLE == 3 + return &bfin_serial3_device; +#endif +} + +void bfin_serial_initialize(void) +{ +#ifdef UART0_RBR + serial_register(&bfin_serial0_device); +#endif +#ifdef UART1_RBR + serial_register(&bfin_serial1_device); +#endif +#ifdef UART2_RBR + serial_register(&bfin_serial2_device); +#endif +#ifdef UART3_RBR + serial_register(&bfin_serial3_device); +#endif +} + +#ifdef CONFIG_DEBUG_EARLY_SERIAL +inline void uart_early_putc(uint32_t uart_base, const char c) +{ + /* send a \r for compatibility */ + if (c == '\n') + uart_early_putc(uart_base, '\r'); + + /* wait for the hardware fifo to clear up */ + while (!(_lsr_read(pUART) & THRE)) + continue; + + /* queue the character for transmission */ + bfin_write(&pUART->thr, c); + SSYNC(); +} + +void uart_early_puts(const char *s) +{ + while (*s) + uart_early_putc(UART_BASE, *s++); +} + +/* Symbol for our assembly to call. */ +void _serial_early_set_baud(uint32_t baud) +{ + serial_early_set_baud(UART_BASE, baud); +} + +/* Symbol for our assembly to call. */ +void _serial_early_init(void) +{ + serial_early_init(UART_BASE); +} +#endif + +#elif defined(CONFIG_UART_MEM) + +char serial_logbuf[CONFIG_UART_MEM]; +char *serial_logbuf_head = serial_logbuf; + +int serial_mem_init(void) +{ + serial_logbuf_head = serial_logbuf; + return 0; +} + +void serial_mem_setbrg(void) +{ +} + +int serial_mem_tstc(void) +{ + return 0; +} + +int serial_mem_getc(void) +{ + return 0; +} + +void serial_mem_putc(const char c) +{ + *serial_logbuf_head = c; + if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM) + serial_logbuf_head = serial_logbuf; +} + +void serial_mem_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +struct serial_device bfin_serial_mem_device = { + .name = "bfin_uart_mem", + .start = serial_mem_init, + .setbrg = serial_mem_setbrg, + .getc = serial_mem_getc, + .tstc = serial_mem_tstc, + .putc = serial_mem_putc, + .puts = serial_mem_puts, +}; + + +__weak struct serial_device *default_serial_console(void) +{ + return &bfin_serial_mem_device; +} + +void bfin_serial_initialize(void) +{ + serial_register(&bfin_serial_mem_device); +} +#endif /* CONFIG_UART_MEM */ diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 0bcccf831b..c751dd74c2 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -111,6 +111,9 @@ #ifndef CONFIG_BAUDRATE # define CONFIG_BAUDRATE 57600 #endif +#ifdef CONFIG_UART_CONSOLE +# define CONFIG_BFIN_SERIAL +#endif /* * Debug Settings -- cgit v1.2.3 From 85f2f8f9adb13535cefcbd4987d2e8e5a978ccd4 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 11 Apr 2013 17:42:38 +0800 Subject: blackfin: Add comments for watchdog event initialization. - Add comments for watchdog event initialization. - Make sure the writting operation to MMRs are finished. Signed-off-by: Sonic Zhang --- arch/blackfin/cpu/initcode.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/blackfin/cpu/initcode.c') diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 5fc06e11ff..ffaf1017d7 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -458,15 +458,23 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB) if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { serial_putc('e'); #ifdef __ADSPBF60x__ + /* Reset system event controller */ bfin_write_SEC_GCTL(0x2); + bfin_write_SEC_CCTL(0x2); SSYNC(); + + /* Enable fault event input and system reset action in fault + * controller. Route watchdog timeout event to fault interface. + */ bfin_write_SEC_FCTL(0xc1); + /* Enable watchdog interrupt source */ bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6); - - bfin_write_SEC_CCTL(0x2); SSYNC(); + + /* Enable system event controller */ bfin_write_SEC_GCTL(0x1); bfin_write_SEC_CCTL(0x1); + SSYNC(); #endif bfin_write_WDOG_CTL(WDDIS); SSYNC(); -- cgit v1.2.3