From 3607a8084aa718a10613ec4e5dd467b9300fc0a2 Mon Sep 17 00:00:00 2001
From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Fri, 18 May 2018 22:05:23 +0800
Subject: arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/reset_manager.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'arch/arm/mach-socfpga/reset_manager.c')

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 1389c82169..e0a01ed07a 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -8,8 +8,16 @@
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/mailbox_s10.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
+#endif
 
 /*
  * Write the reset manager register to cause reset
@@ -17,8 +25,13 @@ static const struct socfpga_reset_manager *reset_manager_base =
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+	puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+	mbox_reset_cold();
+#else
 	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
 	       &reset_manager_base->ctrl);
+#endif
 	/*
 	 * infinite loop here as watchdog will trigger and reset
 	 * the processor
-- 
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