From f56e63509985d23e8912beaf3c38b07f7a1b12c6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 23 Nov 2016 13:25:27 +0530 Subject: board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7__OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/mach-omap2/omap5/hw_data.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/mach-omap2/omap5/hw_data.c') diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index c85c71a87c..58991d7d04 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -336,6 +336,22 @@ struct pmic_data tps659038 = { .gpio_en = 0, }; +/* The LP8732 and LP8733 are software-compatible, use common struct */ +struct pmic_data lp8733 = { + .base_offset = LP873X_BUCK_BASE_VOLT_UV, + .step = 5000, /* 5 mV represented in uV */ + /* + * Offset codes 0 - 0x13 Invalid. + * Offset codes 0x14 0x17 give 10mV steps + * Offset codes 0x17 through 0x9D give 5mV steps + * So let us start with our operating range from .73V + */ + .start_code = 0x17, + .i2c_slave_addr = 0x60, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value[OPP_NOM] = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, -- cgit v1.2.3