From 961ac7873520d661d3ad2bf4c6390f21bcad536a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:15 +0800 Subject: imx8ulp: soc: Check the DBD_EN fuse before setting RDC S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC is allowed by all masters. Current S400 has issue if the XRDC has released to A35, then A35 reset will fail in ROM due to S400 fails to get XRDC. So temp work around is checking the DBD_EN, if it is not fused, we don't need to call release XRDC or TRDC. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index bba6323f96..b25f5f2521 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -468,11 +469,22 @@ static int trdc_set_access(void) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { + u32 val = 0; + int ret; + bool rdc_en = true; /* Default assume DBD_EN is set */ + /* Disable wdog */ init_wdog(); + /* Read DBD_EN fuse */ + ret = fuse_read(8, 1, &val); + if (!ret) + rdc_en = !!(val & 0x4000); + if (get_boot_mode() == SINGLE_BOOT) { - release_rdc(RDC_TRDC); + if (rdc_en) + release_rdc(RDC_TRDC); + trdc_set_access(); /* LPAV to APD */ setbits_le32(0x2802B044, BIT(7)); @@ -482,8 +494,10 @@ int arch_cpu_init(void) setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); } - /* release xrdc, then allow A35 to write SRAM2 */ - release_rdc(RDC_XRDC); + /* Release xrdc, then allow A35 to write SRAM2 */ + if (rdc_en) + release_rdc(RDC_XRDC); + xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); clock_init(); -- cgit v1.2.3 From d563d29203de33e2d35b6c39e0e0c7f38cb51f3d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:16 +0800 Subject: arm: imx8ulp: Allocate LPAV resources to AP domain When single boot, assign AP domain as the master domain of the LPAV. Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI eDMA channel and eDMA request to APD Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b25f5f2521..7898cb0ed9 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -466,6 +466,20 @@ static int trdc_set_access(void) return 0; } +void lpav_configure(void) +{ + /* LPAV to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); + + /* GPU 2D/3D/DCNANO/MIPI_DSI to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + /* LPAV slave/dma2 ch allocation and request allocation to APD */ + writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); + writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); + writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); +} + int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { @@ -486,12 +500,8 @@ int arch_cpu_init(void) release_rdc(RDC_TRDC); trdc_set_access(); - /* LPAV to APD */ - setbits_le32(0x2802B044, BIT(7)); - /* GPU 2D/3D to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2)); - /* DCNANO and MIPI_DSI to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + lpav_configure(); } /* Release xrdc, then allow A35 to write SRAM2 */ -- cgit v1.2.3 From 99de168f7e7173748f3a04cbcec1984fb4c8630b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 29 Oct 2021 09:46:17 +0800 Subject: imx8ulp: assign PXP/HIFI4/EPDC to APD domain Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not able to receive interrupts from the modules. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 7898cb0ed9..e0574112cd 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -471,8 +471,8 @@ void lpav_configure(void) /* LPAV to APD */ setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); - /* GPU 2D/3D/DCNANO/MIPI_DSI to APD */ - setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + /* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F); /* LPAV slave/dma2 ch allocation and request allocation to APD */ writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); -- cgit v1.2.3 From 608ed200f1ce5d56ef0c7b1be7177de86462157c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:20 +0800 Subject: imx8ulp: rdc: allow A35 access flexspi0 mem For singel boot, set flexspi0 mem to be accessed by A35 Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e0574112cd..f64a8fb9fc 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -463,6 +463,8 @@ static int trdc_set_access(void) /* Iomuxc0: : PBridge1 slot 33 */ trdc_mbc_set_access(2, 7, 1, 33, false); + /* flexspi0 */ + trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); return 0; } -- cgit v1.2.3 From 9dde390be69bfc80708458796c2554713c66cea4 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:21 +0800 Subject: imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h | 4 ++ arch/arm/mach-imx/imx8ulp/clock.c | 6 +++ arch/arm/mach-imx/imx8ulp/soc.c | 5 +++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 56 ++++++++++++++++++++++++ 4 files changed, 71 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h index d7c07f41b3..d0eefcbc92 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -9,6 +9,10 @@ #include enum { + IMX8ULP_PAD_PTA3__TPM0_CH2 = IOMUX_PAD(0x000c, 0x000c, IOMUX_CONFIG_MPORTS | 0x6, 0x0948, 0x1, 0), + IMX8ULP_PAD_PTA8__LPI2C0_SCL = IOMUX_PAD(0x0020, 0x0020, IOMUX_CONFIG_MPORTS | 0x5, 0x097c, 0x2, 0), + IMX8ULP_PAD_PTA9__LPI2C0_SDA = IOMUX_PAD(0x0024, 0x0024, IOMUX_CONFIG_MPORTS | 0x5, 0x0980, 0x2, 0), + IMX8ULP_PAD_PTB7__PMIC0_MODE2 = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), IMX8ULP_PAD_PTB8__PMIC0_MODE1 = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), IMX8ULP_PAD_PTB9__PMIC0_MODE0 = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 02e90f7856..e599e6c4c6 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -186,6 +186,9 @@ int enable_i2c_clk(unsigned char enable, u32 i2c_num) LPI2C7_PCC4_SLOT << 8 | 4, }; + if (i2c_num == 0) + return 0; + if (i2c_num < 4 || i2c_num > 7) return -EINVAL; @@ -214,6 +217,9 @@ u32 imx_get_i2cclk(u32 i2c_num) LPI2C7_PCC4_SLOT << 8 | 4, }; + if (i2c_num == 0) + return 24000000; + if (i2c_num < 4 || i2c_num > 7) return 0; diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index f64a8fb9fc..427b5e4117 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -465,6 +465,11 @@ static int trdc_set_access(void) /* flexspi0 */ trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); + + /* tpm0: PBridge1 slot 21 */ + trdc_mbc_set_access(2, 7, 1, 21, false); + /* lpi2c0: PBridge1 slot 24 */ + trdc_mbc_set_access(2, 7, 1, 24, false); return 0; } diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 3ff4d43c99..1502e4dbb6 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -12,6 +12,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -48,11 +49,66 @@ int board_phy_config(struct phy_device *phydev) } #endif +#define I2C_PAD_CTRL (PAD_CTL_ODE) +static const iomux_cfg_t lpi2c0_pads[] = { + IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), +}; + +#define TPM_PAD_CTRL (PAD_CTL_DSE) +static const iomux_cfg_t tpm0_pads[] = { + IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL), +}; + +void mipi_dsi_mux_panel(void) +{ + int ret; + struct gpio_desc desc; + + /* It is temp solution to directly access i2c, need change to rpmsg later */ + + /* enable lpi2c0 clock and iomux */ + imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads)); + writel(0xD2000000, 0x28091060); + + ret = dm_gpio_lookup_name("gpio@20_9", &desc); + if (ret) { + printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "dsi_mux"); + if (ret) { + printf("%s request dsi_mux failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +void mipi_dsi_panel_backlight(void) +{ + /* It is temp solution to directly access pwm, need change to rpmsg later */ + imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads)); + writel(0xD4000001, 0x28091054); + + /* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */ + writel(1000, 0x28095018); + writel(1000, 0x28095034); /* MOD = CV, full duty */ + writel(0x28, 0x28095010); + writel(0x20, 0x28095030); +} + int board_init(void) { if (IS_ENABLED(CONFIG_FEC_MXC)) setup_fec(); + if (IS_ENABLED(CONFIG_DM_VIDEO)) { + mipi_dsi_mux_panel(); + mipi_dsi_panel_backlight(); + } + return 0; } -- cgit v1.2.3 From 16062f9b0a566cfa07fed21aef183608de6da50e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:22 +0800 Subject: imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest To avoid DCNANO underrun issue on high loading test, set its read Qos on NIC_LPAV to highest Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 427b5e4117..0cf4765bd6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -485,6 +485,9 @@ void lpav_configure(void) writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); + + /* Set read QoS of dcnano on LPAV NIC */ + writel(0xf, 0x2e447100); } int arch_cpu_init(void) -- cgit v1.2.3 From bd8b673003078309341c81b6a059f3bdebd81c4b Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:23 +0800 Subject: imx8ulp: Fix DCNANO QoS setting The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 3 +++ board/freescale/imx8ulp_evk/spl.c | 3 +++ 3 files changed, 7 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 1a142dce72..8e2c6ed0ce 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -16,4 +16,5 @@ enum bt_mode get_boot_mode(void); int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); int xrdc_config_pdac_openacc(u32 bridge, u32 index); enum boot_device get_boot_device(void); +void set_lpav_qos(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 0cf4765bd6..2348132bf7 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -485,7 +485,10 @@ void lpav_configure(void) writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); +} +void set_lpav_qos(void) +{ /* Set read QoS of dcnano on LPAV NIC */ writel(0xf, 0x2e447100); } diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index faece336ef..42f8e262b6 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -90,6 +90,9 @@ void spl_board_init(void) /* Init XRDC MRC for VIDEO, DSP domains */ xrdc_init_mrc(); + + /* Call it after PS16 power up */ + set_lpav_qos(); } void board_init_f(ulong dummy) -- cgit v1.2.3 From 112b4cac9d9bd986a5c0e267193dff3e46bab68a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:24 +0800 Subject: imx8ulp: Remove freescale name from CPU revision Remove the freescale vendor name from CPU revision print to align with other i.MX platforms Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 2348132bf7..d9dca21e8c 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -211,7 +211,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); -- cgit v1.2.3 From 9c7fbebe5dd5d9daa9160b778432daef2a13f47f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:25 +0800 Subject: imx8ulp: Workaround LPOSC_TRIM fuse load issue 8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 20 ++++++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 6 ++++++ 3 files changed, 27 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 8e2c6ed0ce..284ccafc98 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -17,4 +17,5 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); int xrdc_config_pdac_openacc(u32 bridge, u32 index); enum boot_device get_boot_device(void); void set_lpav_qos(void); +void load_lposc_fuse(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index d9dca21e8c..e12e28d9e7 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -487,6 +487,26 @@ void lpav_configure(void) writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); } +void load_lposc_fuse(void) +{ + int ret; + u32 val = 0, val2 = 0, reg; + + ret = fuse_read(25, 0, &val); + if (ret) + return; /* failed */ + + ret = fuse_read(25, 1, &val2); + if (ret) + return; /* failed */ + + /* LPOSCCTRL */ + reg = readl(0x2802f304); + reg &= ~0xff; + reg |= (val & 0xff); + writel(reg, 0x2802f304); +} + void set_lpav_qos(void) { /* Set read QoS of dcnano on LPAV NIC */ diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index 42f8e262b6..c17d5eff7d 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -77,6 +77,12 @@ void spl_board_init(void) /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ + /* Load the lposc fuse for single boot to work around ROM issue, + * The fuse depends on S400 to read. + */ + if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT) + load_lposc_fuse(); + upower_init(); power_init_board(); -- cgit v1.2.3 From 484b306b9e53d39c87b54376fc4468ff5aa34297 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 29 Oct 2021 09:46:28 +0800 Subject: imx8ulp: Update ethernet mac to get from fuse Get the MAC address from fuse bank5 word 3 and 4. It has MSB first at lowest address, so have a reverse order with other iMX used in mac.c Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e12e28d9e7..943ea7fb7e 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -588,7 +588,30 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { + u32 val[2] = {}; + int ret; + + ret = fuse_read(5, 3, &val[0]); + if (ret) + goto err; + + ret = fuse_read(5, 4, &val[1]); + if (ret) + goto err; + + mac[0] = val[0]; + mac[1] = val[0] >> 8; + mac[2] = val[0] >> 16; + mac[3] = val[0] >> 24; + mac[4] = val[1]; + mac[5] = val[1] >> 8; + + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +err: memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); } int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc; -- cgit v1.2.3 From 6293b73d0ffb90e67cf959360ca72e737290bcd7 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Fri, 29 Oct 2021 09:46:32 +0800 Subject: imx8ulp: implement to obtain the SoC current temperature Obatin the SoC current temperature in print_cpuinfo(). Reviewed-by: Ye Li Signed-off-by: Alice Guo Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/mach-imx/imx8ulp/soc.c') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 943ea7fb7e..934b0ef038 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -216,6 +217,22 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); +#if defined(CONFIG_IMX_PMC_TEMPERATURE) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device(UCLASS_THERMAL, 0, &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + if (!ret) + printf("CPU current temperature: %d\n", temp); + else + debug(" - failed to get CPU current temperature\n"); + } else { + debug(" - failed to get CPU current temperature\n"); + } +#endif + printf("Reset cause: %s\n", get_reset_cause(cause)); printf("Boot mode: "); -- cgit v1.2.3