From a43d46a73cb2c40481791cb292b8eb0b5a80d55e Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 26 Apr 2018 18:21:31 +0530 Subject: arm: v7R: Add support for enabling caches Cache maintenance procedure is same for v7A and v7R processors. So re-use cache-cp15.c file except for mmu parts. Tested-by: Michal Simek Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/lib/cache-cp15.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/lib/cache-cp15.c') diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index febb253f83..0688f1e6a6 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -8,11 +8,13 @@ #include #include #include +#include #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_ARM_MMU __weak void arm_init_before_mmu(void) { } @@ -201,15 +203,23 @@ static int mmu_enabled(void) { return get_cr() & CR_M; } +#endif /* CONFIG_SYS_ARM_MMU */ /* cache_bit must be either CR_I or CR_C */ static void cache_enable(uint32_t cache_bit) { uint32_t reg; - /* The data cache is not active unless the mmu is enabled too */ + /* The data cache is not active unless the mmu/mpu is enabled too */ +#ifdef CONFIG_SYS_ARM_MMU if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); +#elif defined(CONFIG_SYS_ARM_MPU) + if ((cache_bit == CR_C) && !mpu_enabled()) { + printf("Consider enabling MPU before enabling caches\n"); + return; + } +#endif reg = get_cr(); /* get control reg. */ set_cr(reg | cache_bit); } -- cgit v1.2.3