From d2f18c275eef1eaca58919fb34ea0abf3bfbddcd Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 21 Jul 2011 09:09:59 -0400 Subject: omap4: utility function to identify the context of hw init The basic hardware init of OMAP4(s_init()) can happen in 4 different contexts: 1. SPL running from SRAM 2. U-Boot running from FLASH 3. Non-XIP U-Boot loaded to SDRAM by SPL 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the Configuration Header feature What level of hw initialization gets done depends on this context. Add a utility function to find this context. Signed-off-by: Aneesh V Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/omap_common.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm/include/asm/omap_common.h (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h new file mode 100644 index 0000000000..d80f665079 --- /dev/null +++ b/arch/arm/include/asm/omap_common.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP_COMMON_H_ +#define _OMAP_COMMON_H_ + +/* HW Init Context */ +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +#endif /* _OMAP_COMMON_H_ */ -- cgit v1.2.3 From 3776801d0ae4c147cba3110f71441edefe46a02c Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 21 Jul 2011 09:10:07 -0400 Subject: omap4: add clock support Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules 3. Setting up the right voltage on voltage rails This work draws upon previous work done for x-loader by: Santosh Shilimkar Rajendra Nayak Signed-off-by: Aneesh V Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/omap4/Makefile | 1 + arch/arm/cpu/armv7/omap4/board.c | 1 + arch/arm/cpu/armv7/omap4/clocks.c | 809 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/clocks.h | 664 +++++++++++++++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 8 + arch/arm/include/asm/omap_common.h | 3 + tools/omap/clocks_get_m_n.c | 197 +++++++ 7 files changed, 1683 insertions(+) create mode 100644 arch/arm/cpu/armv7/omap4/clocks.c create mode 100644 arch/arm/include/asm/arch-omap4/clocks.h create mode 100644 tools/omap/clocks_get_m_n.c (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 987dc9d78c..ac4b2a6119 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).o SOBJS += lowlevel_init.o COBJS += board.o +COBJS += clocks.o COBJS += mem.o COBJS += sys_info.o diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 09861a99f5..1c26a66b79 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -154,6 +154,7 @@ void s_init(void) init_omap4_revision(); watchdog_init(); set_mux_conf_regs(); + prcm_init(); } /* diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c new file mode 100644 index 0000000000..e8d3a52440 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -0,0 +1,809 @@ +/* + * + * Clock initialization for OMAP4 + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * Based on previous work by: + * Santosh Shilimkar + * Rajendra Nayak + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +#ifndef CONFIG_SPL_BUILD +/* + * printing to console doesn't work unless + * this code is executed from SPL + */ +#define printf(fmt, args...) +#define puts(s) +#endif + +#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) + +struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; + +static const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 13000000, /* 13 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ +}; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */ +static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { + {66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ + {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1 +}; + + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static inline u32 __get_sys_clk_index(void) +{ + u32 ind; + /* + * For ES1 the ROM code calibration of sys clock is not reliable + * due to hw issue. So, use hard-coded value. If this value is not + * correct for any board over-ride this function in board file + * From ES2.0 onwards you will get this information from + * CM_SYS_CLKSEL + */ + if (omap_revision() == OMAP4430_ES1_0) + ind = OMAP_SYS_CLK_IND_38_4_MHZ; + else { + /* SYS_CLKSEL - 1 to match the dpll param array indices */ + ind = (readl(&prcm->cm_sys_clksel) & + CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + } + return ind; +} + +u32 get_sys_clk_index(void) + __attribute__ ((weak, alias("__get_sys_clk_index"))); + +u32 get_sys_clk_freq(void) +{ + u8 index = get_sys_clk_index(); + return sys_clk_array[index]; +} + +static inline void do_bypass_dpll(u32 *const base) +{ + struct dpll_regs *dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_FAST_RELOCK_BYPASS << + CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, + LDELAY)) { + printf("Bypassing DPLL failed %p\n", base); + } +} + +static inline void do_lock_dpll(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(u32 *const base) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + &dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for %p\n", base); + hang(); + } +} + +static void do_setup_dpll(u32 *const base, const struct dpll_params *params, + u8 lock) +{ + u32 temp; + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + bypass_dpll(base); + + /* Set M & N */ + temp = readl(&dpll_regs->cm_clksel_dpll); + + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, &dpll_regs->cm_clksel_dpll); + + /* Lock */ + if (lock) + do_lock_dpll(base); + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, &dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, &dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, &dpll_regs->cm_div_m6_dpll); + if (params->m7 >= 0) + writel(params->m7, &dpll_regs->cm_div_m7_dpll); + + /* Wait till the DPLL locks */ + if (lock) + wait_for_lock(base); +} + +const struct dpll_params *get_core_dpll_params(void) +{ + u32 sysclk_ind = get_sys_clk_index(); + + switch (omap_revision()) { + case OMAP4430_ES1_0: + return &core_dpll_params_es1_1524mhz[sysclk_ind]; + case OMAP4430_ES2_0: + case OMAP4430_SILICON_ID_INVALID: + /* safest */ + return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; + default: + return &core_dpll_params_1600mhz[sysclk_ind]; + } +} + +u32 omap4_ddr_clk(void) +{ + u32 ddr_clk, sys_clk_khz; + const struct dpll_params *core_dpll_params; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + core_dpll_params = get_core_dpll_params(); + + debug("sys_clk %d\n ", sys_clk_khz * 1000); + + /* Find Core DPLL locked frequency first */ + ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / + (core_dpll_params->n + 1); + /* + * DDR frequency is PHY_ROOT_CLK/2 + * PHY_ROOT_CLK = Fdpll/2/M2 + */ + ddr_clk = ddr_clk / 4 / core_dpll_params->m2; + + ddr_clk *= 1000; /* convert to Hz */ + debug("ddr_clk %d\n ", ddr_clk); + + return ddr_clk; +} + +static void setup_dplls(void) +{ + u32 sysclk_ind, temp; + const struct dpll_params *params; + debug("setup_dplls\n"); + + sysclk_ind = get_sys_clk_index(); + + /* CORE dpll */ + params = get_core_dpll_params(); /* default - safest */ + /* + * Do not lock the core DPLL now. Just set it up. + * Core DPLL will be locked after setting up EMIF + * using the FREQ_UPDATE method(freq_update_core()) + */ + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ + temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | + (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | + (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); + writel(temp, &prcm->cm_clksel_core); + debug("Core DPLL configured\n"); + + /* lock PER dpll */ + do_setup_dpll(&prcm->cm_clkmode_dpll_per, + &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); + debug("PER DPLL locked\n"); + + /* MPU dpll */ + if (omap_revision() == OMAP4430_ES1_0) + params = &mpu_dpll_params_1200mhz[sysclk_ind]; + else + params = &mpu_dpll_params_1584mhz[sysclk_ind]; + do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); + debug("MPU DPLL locked\n"); +} + +static void setup_non_essential_dplls(void) +{ + u32 sys_clk_khz, abe_ref_clk; + u32 sysclk_ind, sd_div, num, den; + const struct dpll_params *params; + + sysclk_ind = get_sys_clk_index(); + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* IVA */ + clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, + CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); + + do_setup_dpll(&prcm->cm_clkmode_dpll_iva, + &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); + + /* + * USB: + * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction + * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) + * - where CLKINP is sys_clk in MHz + * Use CLKINP in KHz and adjust the denominator accordingly so + * that we have enough accuracy and at the same time no overflow + */ + params = &usb_dpll_params_1920mhz[sysclk_ind]; + num = params->m * sys_clk_khz; + den = (params->n + 1) * 250 * 1000; + num += den - 1; + sd_div = num / den; + clrsetbits_le32(&prcm->cm_clksel_dpll_usb, + CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, + sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); + + /* Now setup the dpll with the regular function */ + do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); + +#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK + params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; +#else + params = &abe_dpll_params_32k_196608khz; + abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; + /* + * We need to enable some additional options to achieve + * 196.608MHz from 32768 Hz + */ + setbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| + CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| + CM_CLKMODE_DPLL_LPMODE_EN_MASK| + CM_CLKMODE_DPLL_REGM4XEN_MASK); + /* Spend 4 REFCLK cycles at each stage */ + clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, + CM_CLKMODE_DPLL_RAMP_RATE_MASK, + 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); +#endif + + /* Select the right reference clk */ + clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, + CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, + abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); + /* Lock the dpll */ + do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); +} + +static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) +{ + u32 temp, offset_code; + u32 step = 12660; /* 12.66 mV represented in uV */ + u32 offset = volt_mv; + + /* convert to uV for better accuracy in the calculations */ + offset *= 1000; + + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + /* The code starts at 1 not 0 */ + offset_code++; + + debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, + offset_code); + + temp = SMPS_I2C_SLAVE_ADDR | + (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | + (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | + PRM_VC_VAL_BYPASS_VALID_BIT; + writel(temp, &prcm->prm_vc_val_bypass); + if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, + &prcm->prm_vc_val_bypass, LDELAY)) { + printf("Scaling voltage failed for 0x%x\n", vcore_reg); + } +} + +/* + * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva + * We set the maximum voltages allowed here because Smart-Reflex is not + * enabled in bootloader. Voltage initialization in the kernel will set + * these to the nominal values after enabling Smart-Reflex + */ +static void scale_vcores(void) +{ + u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp; + + sys_clk_khz = get_sys_clk_freq() / 1000; + + /* + * Setup the dedicated I2C controller for Voltage Control + * I2C clk - high period 40% low period 60% + */ + cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; + /* values to be set in register - less by 5 & 7 respectively */ + cycles_hi -= 5; + cycles_low -= 7; + temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | + (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); + writel(temp, &prcm->prm_vc_cfg_i2c_clk); + + /* Disable high speed mode and all advanced features */ + writel(0x0, &prcm->prm_vc_cfg_i2c_mode); + + /* + * VCORE 1 - 4430 : supplies vdd_mpu + * Setting a high voltage for Nitro mode as smart reflex is not enabled. + * We use the maximum possible value in the AVS range because the next + * higher voltage in the discrete range (code >= 0b111010) is way too + * high + */ + volt = 1417; + do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + + /* VCORE 2 - supplies vdd_iva */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + + /* VCORE 3 - supplies vdd_core */ + volt = 1200; + do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - 0x%08x\n", clkctrl_reg); +} + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - 0x%08x\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_basic_clocks(void) +{ + u32 i, max = 100, wait_for_enable = 1; + u32 *const clk_domains_essential[] = { + &prcm->cm_l4per_clkstctrl, + &prcm->cm_l3init_clkstctrl, + &prcm->cm_memif_clkstctrl, + &prcm->cm_l4cfg_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_wkup_gpio1_clkctrl, + &prcm->cm_l4per_gpio2_clkctrl, + &prcm->cm_l4per_gpio3_clkctrl, + &prcm->cm_l4per_gpio4_clkctrl, + &prcm->cm_l4per_gpio5_clkctrl, + &prcm->cm_l4per_gpio6_clkctrl, + &prcm->cm_memif_emif_1_clkctrl, + &prcm->cm_memif_emif_2_clkctrl, + &prcm->cm_l3init_hsusbotg_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_l4cfg_l4_cfg_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_essential[] = { + &prcm->cm_l4per_gptimer2_clkctrl, + &prcm->cm_l3init_hsmmc1_clkctrl, + &prcm->cm_l3init_hsmmc2_clkctrl, + &prcm->cm_l4per_mcspi1_clkctrl, + &prcm->cm_wkup_gptimer1_clkctrl, + &prcm->cm_l4per_i2c1_clkctrl, + &prcm->cm_l4per_i2c2_clkctrl, + &prcm->cm_l4per_i2c3_clkctrl, + &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_l4per_uart3_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains_essential[i]; i++) { + enable_clock_domain(clk_domains_essential[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) { + enable_clock_module(clk_modules_hw_auto_essential[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) { + enable_clock_module(clk_modules_explicit_en_essential[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains_essential[i]; i++) { + enable_clock_domain(clk_domains_essential[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +static void enable_non_essential_clocks(void) +{ + u32 i, max = 100, wait_for_enable = 0; + u32 *const clk_domains_non_essential[] = { + &prcm->cm_mpu_m3_clkstctrl, + &prcm->cm_ivahd_clkstctrl, + &prcm->cm_dsp_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sgx_clkstctrl, + &prcm->cm1_abe_clkstctrl, + &prcm->cm_c2c_clkstctrl, + &prcm->cm_cam_clkstctrl, + &prcm->cm_dss_clkstctrl, + &prcm->cm_sdma_clkstctrl, + 0 + }; + + u32 *const clk_modules_hw_auto_non_essential[] = { + &prcm->cm_mpu_m3_mpu_m3_clkctrl, + &prcm->cm_ivahd_ivahd_clkctrl, + &prcm->cm_ivahd_sl2_clkctrl, + &prcm->cm_dsp_dsp_clkctrl, + &prcm->cm_l3_2_gpmc_clkctrl, + &prcm->cm_l3instr_l3_3_clkctrl, + &prcm->cm_l3instr_l3_instr_clkctrl, + &prcm->cm_l3instr_intrconn_wp1_clkctrl, + &prcm->cm_l3init_hsi_clkctrl, + &prcm->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 *const clk_modules_explicit_en_non_essential[] = { + &prcm->cm1_abe_aess_clkctrl, + &prcm->cm1_abe_pdm_clkctrl, + &prcm->cm1_abe_dmic_clkctrl, + &prcm->cm1_abe_mcasp_clkctrl, + &prcm->cm1_abe_mcbsp1_clkctrl, + &prcm->cm1_abe_mcbsp2_clkctrl, + &prcm->cm1_abe_mcbsp3_clkctrl, + &prcm->cm1_abe_slimbus_clkctrl, + &prcm->cm1_abe_timer5_clkctrl, + &prcm->cm1_abe_timer6_clkctrl, + &prcm->cm1_abe_timer7_clkctrl, + &prcm->cm1_abe_timer8_clkctrl, + &prcm->cm1_abe_wdt3_clkctrl, + &prcm->cm_l4per_gptimer9_clkctrl, + &prcm->cm_l4per_gptimer10_clkctrl, + &prcm->cm_l4per_gptimer11_clkctrl, + &prcm->cm_l4per_gptimer3_clkctrl, + &prcm->cm_l4per_gptimer4_clkctrl, + &prcm->cm_l4per_hdq1w_clkctrl, + &prcm->cm_l4per_mcbsp4_clkctrl, + &prcm->cm_l4per_mcspi2_clkctrl, + &prcm->cm_l4per_mcspi3_clkctrl, + &prcm->cm_l4per_mcspi4_clkctrl, + &prcm->cm_l4per_mmcsd3_clkctrl, + &prcm->cm_l4per_mmcsd4_clkctrl, + &prcm->cm_l4per_mmcsd5_clkctrl, + &prcm->cm_l4per_uart1_clkctrl, + &prcm->cm_l4per_uart2_clkctrl, + &prcm->cm_l4per_uart4_clkctrl, + &prcm->cm_wkup_keyboard_clkctrl, + &prcm->cm_wkup_wdtimer2_clkctrl, + &prcm->cm_cam_iss_clkctrl, + &prcm->cm_cam_fdif_clkctrl, + &prcm->cm_dss_dss_clkctrl, + &prcm->cm_sgx_sgx_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, + &prcm->cm_l3init_fsusb_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { + enable_clock_domain(clk_domains_non_essential[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in HW_AUTO */ + for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { + enable_clock_module(clk_modules_hw_auto_non_essential[i], + MODULE_CLKCTRL_MODULEMODE_HW_AUTO, + wait_for_enable); + }; + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; + i++) { + enable_clock_module(clk_modules_explicit_en_non_essential[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; + + /* Put the clock domains in HW_AUTO mode now */ + for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { + enable_clock_domain(clk_domains_non_essential[i], + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + } + + /* Put camera module in no sleep mode */ + clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + + +void freq_update_core(void) +{ + u32 freq_config1 = 0; + const struct dpll_params *core_dpll_params; + + core_dpll_params = get_core_dpll_params(); + /* Put EMIF clock domain in sw wakeup mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + + freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | + SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; + + freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & + SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; + + freq_config1 |= (core_dpll_params->m2 << + SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & + SHADOW_FREQ_CONFIG1_M2_DIV_MASK; + + writel(freq_config1, &prcm->cm_shadow_freq_config1); + if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, + &prcm->cm_shadow_freq_config1, LDELAY)) { + puts("FREQ UPDATE procedure failed!!"); + hang(); + } + + /* Put EMIF clock domain back in hw auto mode */ + enable_clock_domain(&prcm->cm_memif_clkstctrl, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO); + wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); + wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); +} + +void bypass_dpll(u32 *const base) +{ + do_bypass_dpll(base); + wait_for_bypass(base); +} + +void lock_dpll(u32 *const base) +{ + do_lock_dpll(base); + wait_for_lock(base); +} + +void prcm_init(void) +{ + switch (omap4_hw_init_context()) { + case OMAP_INIT_CONTEXT_SPL: + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: + scale_vcores(); + setup_dplls(); + enable_basic_clocks(); + setup_non_essential_dplls(); + enable_non_essential_clocks(); + break; + default: + break; + } +} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h new file mode 100644 index 0000000000..71db39c8c9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -0,0 +1,664 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ +#include + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) +#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) +#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) +#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) + +struct omap4_prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 pad001[1]; + u32 cm_clksel_abe; + u32 pad002[1]; + u32 cm_dll_ctrl; + u32 pad003[3]; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 pad004[3]; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 pad005[5]; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 pad006[3]; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 pad007[2]; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 pad008[2]; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 pad009[3]; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 pad010[4]; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 pad011[4]; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 pad012[1]; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 pad013[1]; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 pad014[5]; + u32 cm_shadow_freq_config1; + + /* cm1.dsp */ + u32 pad015[103]; + u32 cm_dsp_clkstctrl; + u32 pad016[7]; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 pad017[55]; + u32 cm1_abe_clkstctrl; + u32 pad018[7]; + u32 cm1_abe_l4abe_clkctrl; + u32 pad019[1]; + u32 cm1_abe_aess_clkctrl; + u32 pad020[1]; + u32 cm1_abe_pdm_clkctrl; + u32 pad021[1]; + u32 cm1_abe_dmic_clkctrl; + u32 pad022[1]; + u32 cm1_abe_mcasp_clkctrl; + u32 pad023[1]; + u32 cm1_abe_mcbsp1_clkctrl; + u32 pad024[1]; + u32 cm1_abe_mcbsp2_clkctrl; + u32 pad025[1]; + u32 cm1_abe_mcbsp3_clkctrl; + u32 pad026[1]; + u32 cm1_abe_slimbus_clkctrl; + u32 pad027[1]; + u32 cm1_abe_timer5_clkctrl; + u32 pad028[1]; + u32 cm1_abe_timer6_clkctrl; + u32 pad029[1]; + u32 cm1_abe_timer7_clkctrl; + u32 pad030[1]; + u32 cm1_abe_timer8_clkctrl; + u32 pad031[1]; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 pad032[3805]; + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 pad033[1]; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 pad034[1]; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 pad035[1]; + u32 cm_iva_dvfs_current; + u32 pad036[1]; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 pad037[3]; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 pad038[5]; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 pad039[1]; + u32 cm_clkdcoldo_dpll_usb; + u32 pad040[2]; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 pad041[5]; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + + /* cm2.core */ + u32 pad0411[324]; + u32 cm_l3_1_clkstctrl; + u32 pad042[1]; + u32 cm_l3_1_dynamicdep; + u32 pad043[5]; + u32 cm_l3_1_l3_1_clkctrl; + u32 pad044[55]; + u32 cm_l3_2_clkstctrl; + u32 pad045[1]; + u32 cm_l3_2_dynamicdep; + u32 pad046[5]; + u32 cm_l3_2_l3_2_clkctrl; + u32 pad047[1]; + u32 cm_l3_2_gpmc_clkctrl; + u32 pad048[1]; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 pad049[51]; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 pad050[5]; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 pad051[55]; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 pad052[5]; + u32 cm_sdma_sdma_clkctrl; + u32 pad053[55]; + u32 cm_memif_clkstctrl; + u32 pad054[7]; + u32 cm_memif_dmm_clkctrl; + u32 pad055[1]; + u32 cm_memif_emif_fw_clkctrl; + u32 pad056[1]; + u32 cm_memif_emif_1_clkctrl; + u32 pad057[1]; + u32 cm_memif_emif_2_clkctrl; + u32 pad058[1]; + u32 cm_memif_dll_clkctrl; + u32 pad059[3]; + u32 cm_memif_emif_h1_clkctrl; + u32 pad060[1]; + u32 cm_memif_emif_h2_clkctrl; + u32 pad061[1]; + u32 cm_memif_dll_h_clkctrl; + u32 pad062[39]; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 pad063[5]; + u32 cm_c2c_sad2d_clkctrl; + u32 pad064[1]; + u32 cm_c2c_modem_icr_clkctrl; + u32 pad065[1]; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 pad066[51]; + u32 cm_l4cfg_clkstctrl; + u32 pad067[1]; + u32 cm_l4cfg_dynamicdep; + u32 pad068[5]; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 pad069[1]; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 pad070[1]; + u32 cm_l4cfg_mailbox_clkctrl; + u32 pad071[1]; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 pad072[49]; + u32 cm_l3instr_clkstctrl; + u32 pad073[7]; + u32 cm_l3instr_l3_3_clkctrl; + u32 pad074[1]; + u32 cm_l3instr_l3_instr_clkctrl; + u32 pad075[5]; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + + /* cm2.ivahd */ + u32 pad076[47]; + u32 cm_ivahd_clkstctrl; + u32 pad077[7]; + u32 cm_ivahd_ivahd_clkctrl; + u32 pad078[1]; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 pad079[53]; + u32 cm_cam_clkstctrl; + u32 pad080[7]; + u32 cm_cam_iss_clkctrl; + u32 pad081[1]; + u32 cm_cam_fdif_clkctrl; + + /* cm2.dss */ + u32 pad082[53]; + u32 cm_dss_clkstctrl; + u32 pad083[7]; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 pad084[55]; + u32 cm_sgx_clkstctrl; + u32 pad085[7]; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 pad086[55]; + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 pad087[9]; + u32 cm_l3init_hsmmc1_clkctrl; + u32 pad088[1]; + u32 cm_l3init_hsmmc2_clkctrl; + u32 pad089[1]; + u32 cm_l3init_hsi_clkctrl; + u32 pad090[7]; + u32 cm_l3init_hsusbhost_clkctrl; + u32 pad091[1]; + u32 cm_l3init_hsusbotg_clkctrl; + u32 pad092[1]; + u32 cm_l3init_hsusbtll_clkctrl; + u32 pad093[3]; + u32 cm_l3init_p1500_clkctrl; + u32 pad094[21]; + u32 cm_l3init_fsusb_clkctrl; + u32 pad095[3]; + u32 cm_l3init_usbphy_clkctrl; + + /* cm2.l4per */ + u32 pad096[7]; + u32 cm_l4per_clkstctrl; + u32 pad097[1]; + u32 cm_l4per_dynamicdep; + u32 pad098[5]; + u32 cm_l4per_adc_clkctrl; + u32 pad100[1]; + u32 cm_l4per_gptimer10_clkctrl; + u32 pad101[1]; + u32 cm_l4per_gptimer11_clkctrl; + u32 pad102[1]; + u32 cm_l4per_gptimer2_clkctrl; + u32 pad103[1]; + u32 cm_l4per_gptimer3_clkctrl; + u32 pad104[1]; + u32 cm_l4per_gptimer4_clkctrl; + u32 pad105[1]; + u32 cm_l4per_gptimer9_clkctrl; + u32 pad106[1]; + u32 cm_l4per_elm_clkctrl; + u32 pad107[1]; + u32 cm_l4per_gpio2_clkctrl; + u32 pad108[1]; + u32 cm_l4per_gpio3_clkctrl; + u32 pad109[1]; + u32 cm_l4per_gpio4_clkctrl; + u32 pad110[1]; + u32 cm_l4per_gpio5_clkctrl; + u32 pad111[1]; + u32 cm_l4per_gpio6_clkctrl; + u32 pad112[1]; + u32 cm_l4per_hdq1w_clkctrl; + u32 pad113[1]; + u32 cm_l4per_hecc1_clkctrl; + u32 pad114[1]; + u32 cm_l4per_hecc2_clkctrl; + u32 pad115[1]; + u32 cm_l4per_i2c1_clkctrl; + u32 pad116[1]; + u32 cm_l4per_i2c2_clkctrl; + u32 pad117[1]; + u32 cm_l4per_i2c3_clkctrl; + u32 pad118[1]; + u32 cm_l4per_i2c4_clkctrl; + u32 pad119[1]; + u32 cm_l4per_l4per_clkctrl; + u32 pad1191[3]; + u32 cm_l4per_mcasp2_clkctrl; + u32 pad120[1]; + u32 cm_l4per_mcasp3_clkctrl; + u32 pad121[1]; + u32 cm_l4per_mcbsp4_clkctrl; + u32 pad122[1]; + u32 cm_l4per_mgate_clkctrl; + u32 pad123[1]; + u32 cm_l4per_mcspi1_clkctrl; + u32 pad124[1]; + u32 cm_l4per_mcspi2_clkctrl; + u32 pad125[1]; + u32 cm_l4per_mcspi3_clkctrl; + u32 pad126[1]; + u32 cm_l4per_mcspi4_clkctrl; + u32 pad127[5]; + u32 cm_l4per_mmcsd3_clkctrl; + u32 pad128[1]; + u32 cm_l4per_mmcsd4_clkctrl; + u32 pad129[1]; + u32 cm_l4per_msprohg_clkctrl; + u32 pad130[1]; + u32 cm_l4per_slimbus2_clkctrl; + u32 pad131[1]; + u32 cm_l4per_uart1_clkctrl; + u32 pad132[1]; + u32 cm_l4per_uart2_clkctrl; + u32 pad133[1]; + u32 cm_l4per_uart3_clkctrl; + u32 pad134[1]; + u32 cm_l4per_uart4_clkctrl; + u32 pad135[1]; + u32 cm_l4per_mmcsd5_clkctrl; + u32 pad136[1]; + u32 cm_l4per_i2c5_clkctrl; + u32 pad137[5]; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 pad138[5]; + u32 cm_l4sec_aes1_clkctrl; + u32 pad139[1]; + u32 cm_l4sec_aes2_clkctrl; + u32 pad140[1]; + u32 cm_l4sec_des3des_clkctrl; + u32 pad141[1]; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 pad142[1]; + u32 cm_l4sec_rng_clkctrl; + u32 pad143[1]; + u32 cm_l4sec_sha2md51_clkctrl; + u32 pad144[3]; + u32 cm_l4sec_cryptodma_clkctrl; + u32 pad145[776841]; + + /* l4 wkup regs */ + u32 pad201[6211]; + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 pad202[1467]; + u32 cm_wkup_clkstctrl; + u32 pad203[7]; + u32 cm_wkup_l4wkup_clkctrl; + u32 pad204; + u32 cm_wkup_wdtimer1_clkctrl; + u32 pad205; + u32 cm_wkup_wdtimer2_clkctrl; + u32 pad206; + u32 cm_wkup_gpio1_clkctrl; + u32 pad207; + u32 cm_wkup_gptimer1_clkctrl; + u32 pad208; + u32 cm_wkup_gptimer12_clkctrl; + u32 pad209; + u32 cm_wkup_synctimer_clkctrl; + u32 pad210; + u32 cm_wkup_usim_clkctrl; + u32 pad211; + u32 cm_wkup_sarram_clkctrl; + u32 pad212[5]; + u32 cm_wkup_keyboard_clkctrl; + u32 pad213; + u32 cm_wkup_rtc_clkctrl; + u32 pad214; + u32 cm_wkup_bandgap_clkctrl; + u32 pad215[197]; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_channel; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + +}; + +/* DPLL register offsets */ +#define CM_CLKMODE_DPLL 0 +#define CM_IDLEST_DPLL 0x4 +#define CM_AUTOIDLE_DPLL 0x8 +#define CM_CLKSEL_DPLL 0xC +#define CM_DIV_M2_DPLL 0x10 +#define CM_DIV_M3_DPLL 0x14 +#define CM_DIV_M4_DPLL 0x18 +#define CM_DIV_M5_DPLL 0x1C +#define CM_DIV_M6_DPLL 0x20 +#define CM_DIV_M7_DPLL 0x24 + +#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +#define OMAP4_DPLL_MAX_N 127 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* Clock frequencies */ +#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 +#define OMAP_32K_CLK_FREQ 32768 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#define NUM_SYS_CLKS 7 + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; + u32 cm_div_m7_dpll; +}; + +/* DPLL parameter table */ +struct dpll_params { + u32 m; + u32 n; + u8 m2; + u8 m3; + u8 m4; + u8 m5; + u8 m6; + u8 m7; +}; + +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index c10fa18700..f871921d4a 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -22,6 +22,7 @@ #define _SYS_PROTO_H_ #include +#include #include #include #include @@ -31,6 +32,8 @@ struct omap_sysinfo { }; extern const struct omap_sysinfo sysinfo; +extern struct omap4_prcm_regs *const prcm; + void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); @@ -41,6 +44,11 @@ u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); void omap_rev_string(char *omap4_rev_string); +void prcm_init(void); +void bypass_dpll(u32 *const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); static inline u32 running_from_sdram(void) { diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d80f665079..33caa4e6cc 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,9 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_ +/* Max value for DPLL multiplier M */ +#define OMAP_DPLL_MAX_N 127 + /* HW Init Context */ #define OMAP_INIT_CONTEXT_SPL 0 #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 diff --git a/tools/omap/clocks_get_m_n.c b/tools/omap/clocks_get_m_n.c new file mode 100644 index 0000000000..cfc176042a --- /dev/null +++ b/tools/omap/clocks_get_m_n.c @@ -0,0 +1,197 @@ +/* + * Program for finding M & N values for DPLLs + * To be run on Host PC + * + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +typedef unsigned int u32; +#define MAX_N 127 + +/* + * get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N) + * values based on the reference frequency, required output frequency, + * maximum tolerance for output frequency etc. + * + * target_freq_khz - output frequency required in KHz + * ref_freq_khz - reference(input) frequency in KHz + * m - pointer to computed M value + * n - pointer to computed N value + * tolerance_khz - tolerance for the output frequency. When the algorithm + * succeeds in finding vialble M and N values the corresponding output + * frequency will be in the range: + * [target_freq_khz - tolerance_khz, target_freq_khz] + * + * Formula: + * Fdpll = (2 * M * Fref) / (N + 1) + * + * Considerations for lock-time: + * - Smaller the N, better lock-time, especially lock-time will be + * - For acceptable lock-times: + * Fref / (M + 1) >= 1 MHz + * + * Considerations for power: + * - The difference in power for different N values giving the same + * output is negligible. So, we optimize for lock-time + * + * Hard-constraints: + * - N can not be greater than 127(7 bit field for representing N) + * + * Usage: + * $ gcc clocks_get_m_n.c + * $ ./a.out + */ +int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, + u32 tolerance_khz) +{ + u32 min_freq = target_freq_khz - tolerance_khz; + u32 max_freq = target_freq_khz; + u32 freq, freq_old; + *n = 1; + while (1) { + *m = min_freq / ref_freq_khz / 2 * (*n) ; + freq_old = 0; + while (1) { + freq = ref_freq_khz * 2 * (*m) / (*n); + if (abs(target_freq_khz - freq_old) <= + abs(target_freq_khz - freq)) { + freq = freq_old; + (*m)--; + break; + } + (*m)++; + freq_old = freq; + } + if (freq >= min_freq && freq <= max_freq) + break; + (*n)++; + if ((*n) > MAX_N + 1) { + printf("ref %d m %d n %d target %d : ", + ref_freq_khz, *m, *n, target_freq_khz); + printf("can not find m & n - please consider" + " increasing tolerance\n"); + return -1; + } + } + (*n)--; + printf("ref %d m %d n %d target %d locked %d\n", + ref_freq_khz, *m, *n, target_freq_khz, freq); + if ((ref_freq_khz / (*n + 1)) < 1000) { + printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than" + " ideal, locking time will be high!\n"); + } + return 0; +} + +void main(void) +{ + u32 m, n; + printf("\nMPU - 2000000\n"); + get_m_n_optimized(2000000, 12000, &m, &n, 0); + get_m_n_optimized(2000000, 13000, &m, &n, 0); + get_m_n_optimized(2000000, 16800, &m, &n, 800); + get_m_n_optimized(2000000, 19200, &m, &n, 0); + get_m_n_optimized(2000000, 26000, &m, &n, 0); + get_m_n_optimized(2000000, 27000, &m, &n, 0); + get_m_n_optimized(2000000, 38400, &m, &n, 0); + + printf("\nMPU - 1200000\n"); + get_m_n_optimized(1200000, 12000, &m, &n, 0); + get_m_n_optimized(1200000, 13000, &m, &n, 0); + get_m_n_optimized(1200000, 16800, &m, &n, 800); + get_m_n_optimized(1200000, 19200, &m, &n, 0); + get_m_n_optimized(1200000, 26000, &m, &n, 0); + get_m_n_optimized(1200000, 27000, &m, &n, 0); + get_m_n_optimized(1200000, 38400, &m, &n, 0); + + printf("\nMPU - 1584000\n"); + get_m_n_optimized(1584000, 12000, &m, &n, 0); + get_m_n_optimized(1584000, 13000, &m, &n, 0); + get_m_n_optimized(1584000, 16800, &m, &n, 400); + get_m_n_optimized(1584000, 19200, &m, &n, 0); + get_m_n_optimized(1584000, 26000, &m, &n, 0); + get_m_n_optimized(1584000, 27000, &m, &n, 0); + get_m_n_optimized(1584000, 38400, &m, &n, 0); + + printf("\nCore 1600000\n"); + get_m_n_optimized(1600000, 12000, &m, &n, 0); + get_m_n_optimized(1600000, 13000, &m, &n, 0); + get_m_n_optimized(1600000, 16800, &m, &n, 200); + get_m_n_optimized(1600000, 19200, &m, &n, 0); + get_m_n_optimized(1600000, 26000, &m, &n, 0); + get_m_n_optimized(1600000, 27000, &m, &n, 0); + get_m_n_optimized(1600000, 38400, &m, &n, 0); + + printf("\nPER 1536000\n"); + get_m_n_optimized(1536000, 12000, &m, &n, 0); + get_m_n_optimized(1536000, 13000, &m, &n, 0); + get_m_n_optimized(1536000, 16800, &m, &n, 0); + get_m_n_optimized(1536000, 19200, &m, &n, 0); + get_m_n_optimized(1536000, 26000, &m, &n, 0); + get_m_n_optimized(1536000, 27000, &m, &n, 0); + get_m_n_optimized(1536000, 38400, &m, &n, 0); + + printf("\nIVA 1862000\n"); + get_m_n_optimized(1862000, 12000, &m, &n, 0); + get_m_n_optimized(1862000, 13000, &m, &n, 0); + get_m_n_optimized(1862000, 16800, &m, &n, 0); + get_m_n_optimized(1862000, 19200, &m, &n, 900); + get_m_n_optimized(1862000, 26000, &m, &n, 0); + get_m_n_optimized(1862000, 27000, &m, &n, 0); + get_m_n_optimized(1862000, 38400, &m, &n, 800); + + printf("\nABE 196608 sys clk\n"); + get_m_n_optimized(196608, 12000, &m, &n, 700); + get_m_n_optimized(196608, 13000, &m, &n, 200); + get_m_n_optimized(196608, 16800, &m, &n, 700); + get_m_n_optimized(196608, 19200, &m, &n, 400); + get_m_n_optimized(196608, 26000, &m, &n, 200); + get_m_n_optimized(196608, 27000, &m, &n, 900); + get_m_n_optimized(196608, 38400, &m, &n, 0); + + printf("\nABE 196608 32K\n"); + get_m_n_optimized(196608000/4, 32768, &m, &n, 0); + + printf("\nUSB 1920000\n"); + get_m_n_optimized(1920000, 12000, &m, &n, 0); + get_m_n_optimized(1920000, 13000, &m, &n, 0); + get_m_n_optimized(1920000, 16800, &m, &n, 0); + get_m_n_optimized(1920000, 19200, &m, &n, 0); + get_m_n_optimized(1920000, 26000, &m, &n, 0); + get_m_n_optimized(1920000, 27000, &m, &n, 0); + get_m_n_optimized(1920000, 38400, &m, &n, 0); + + printf("\nCore ES1 1523712\n"); + get_m_n_optimized(1524000, 12000, &m, &n, 100); + get_m_n_optimized(1524000, 13000, &m, &n, 0); + get_m_n_optimized(1524000, 16800, &m, &n, 0); + get_m_n_optimized(1524000, 19200, &m, &n, 0); + get_m_n_optimized(1524000, 26000, &m, &n, 0); + get_m_n_optimized(1524000, 27000, &m, &n, 0); + + /* exact recommendation for SDPs */ + get_m_n_optimized(1523712, 38400, &m, &n, 0); + +} -- cgit v1.2.3 From bcae72116257201d7288cb8c525a29aea4875b95 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 21 Jul 2011 09:10:21 -0400 Subject: omap: add basic SPL support - Provide alternate implementations of board_init_f() board_init_r() for OMAP spl. - Provide linker script - Initialize global data - Add serial console support - Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move it to board config header from config.mk Signed-off-by: Aneesh V Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/Makefile | 7 ++- arch/arm/cpu/armv7/omap-common/Makefile | 4 ++ arch/arm/cpu/armv7/omap-common/spl.c | 82 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 62 ++++++++++++++++++++ arch/arm/cpu/armv7/omap4/Makefile | 5 +- arch/arm/cpu/armv7/omap4/board.c | 7 +++ arch/arm/cpu/armv7/omap4/clocks.c | 33 +++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 2 + board/ti/panda/Makefile | 2 + board/ti/panda/config.mk | 31 ---------- board/ti/sdp4430/Makefile | 2 + board/ti/sdp4430/config.mk | 31 ---------- include/configs/omap4_panda.h | 26 +++++++++ include/configs/omap4_sdp4430.h | 26 +++++++++ 15 files changed, 257 insertions(+), 64 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/spl.c create mode 100644 arch/arm/cpu/armv7/omap-common/u-boot-spl.lds delete mode 100644 board/ti/panda/config.mk delete mode 100644 board/ti/sdp4430/config.mk (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 299792ac5a..92a5a96800 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -26,7 +26,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START := start.o -COBJS := cpu.o cache_v7.o + +ifndef CONFIG_SPL_BUILD +COBJS += cache_v7.o +COBJS += cpu.o +endif + COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 8f698f841d..07087964e6 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -30,6 +30,10 @@ SOBJS := reset.o COBJS := timer.o COBJS += utils.o +ifdef CONFIG_SPL_BUILD +COBJS += spl.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c new file mode 100644 index 0000000000..b2015431e3 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +inline void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +void board_init_f(ulong dummy) +{ + /* + * We call relocate_code() with relocation target same as the + * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting + * skipped. Instead, only .bss initialization will happen. That's + * all we need + */ + debug(">>board_init_f()\n"); + relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); +} + +void board_init_r(gd_t *id, ulong dummy) +{ + for (;;) + ; +} + +void preloader_console_init(void) +{ + const char *u_boot_rev = U_BOOT_VERSION; + char rev_string_buffer[50]; + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + + setup_clocks_for_console(); + serial_init(); /* serial communications setup */ + + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + + printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, + U_BOOT_TIME); + omap_rev_string(rev_string_buffer); + printf("Texas Instruments %s\n", rev_string_buffer); +} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds new file mode 100644 index 0000000000..8867e0604d --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram +} diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index e1ccd68192..e7ee0b8c0a 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -30,9 +30,12 @@ SOBJS += lowlevel_init.o COBJS += board.o COBJS += clocks.o COBJS += emif.o -COBJS += mem.o COBJS += sdram_elpida.o + +ifndef CONFIG_SPL_BUILD +COBJS += mem.o COBJS += sys_info.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 786c239794..54dd509194 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -155,7 +155,14 @@ void s_init(void) init_omap4_revision(); watchdog_init(); set_mux_conf_regs(); +#ifdef CONFIG_SPL_BUILD + preloader_console_init(); +#endif prcm_init(); +#ifdef CONFIG_SPL_BUILD + /* For regular u-boot sdram_init() is called from dram_init() */ + sdram_init(); +#endif } /* diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index e8d3a52440..f1e233a10e 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -791,6 +791,39 @@ void lock_dpll(u32 *const base) wait_for_lock(base); } +void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable all UARTs - console will be on one of them */ + clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_HW_AUTO << + CD_CLKCTRL_CLKTRCTRL_SHIFT); +} + void prcm_init(void) { switch (omap4_hw_init_context()) { diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 1e62878ea4..a81f8e5c24 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -44,6 +44,7 @@ u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); void omap_rev_string(char *omap4_rev_string); +void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 *const base); void freq_update_core(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 33caa4e6cc..69d53d2c72 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -34,4 +34,6 @@ #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 +void preloader_console_init(void); + #endif /* _OMAP_COMMON_H_ */ diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile index 2186403732..09f88ee86d 100644 --- a/board/ti/panda/Makefile +++ b/board/ti/panda/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := panda.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk deleted file mode 100644 index 33901a77b5..0000000000 --- a/board/ti/panda/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments Incorporated, -# -# OMAP 4430 SDP -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# SDRAM Address Space: -# 8000'0000 - 9fff'ffff (512 MB) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile index f1ee5448ed..12f2743d49 100644 --- a/board/ti/sdp4430/Makefile +++ b/board/ti/sdp4430/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := sdp.o cmd_bat.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk deleted file mode 100644 index 33901a77b5..0000000000 --- a/board/ti/sdp4430/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments Incorporated, -# -# OMAP 4430 SDP -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# SDRAM Address Space: -# 8000'0000 - 9fff'ffff (512 MB) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x80e80000 diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index a8dd861126..1112362b32 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -243,4 +243,30 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40304350 +#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 534f89a5e7..6a6be9e9b8 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -249,4 +249,30 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40304350 +#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 8cf686e19b6922a2a6b401af188dfb83414c3c04 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 21 Jul 2011 09:10:27 -0400 Subject: omap: add MMC and FAT support to SPL - Add MMC raw and FAT mode boot support for OMAP - Provide a means by which parameters passed by ROM-code can be saved in u-boot. - Save boot mode related information passed by OMAP4 ROM-code and use it to determine where to load the u-boot from - Assumes that the image has a mkimage header. Gets the payload size and load address from this header. If the header is not detected assume u-boot.bin as payload Signed-off-by: Aneesh V Signed-off-by: Sandeep Paulraj --- arch/arm/cpu/armv7/cpu.c | 7 ++ arch/arm/cpu/armv7/omap-common/spl.c | 194 ++++++++++++++++++++++++++++++- arch/arm/cpu/armv7/omap4/board.c | 21 ++++ arch/arm/cpu/armv7/omap4/lowlevel_init.S | 31 +++++ arch/arm/cpu/armv7/start.S | 1 + arch/arm/include/asm/arch-omap4/omap4.h | 8 ++ arch/arm/include/asm/omap_common.h | 17 +++ include/configs/omap4_panda.h | 5 + include/configs/omap4_sdp4430.h | 5 + 9 files changed, 287 insertions(+), 2 deletions(-) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index def9ced64f..091e3e0842 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -37,6 +37,13 @@ #include #include +void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + __attribute__((weak, alias("save_boot_params_default"))); + int cleanup_before_linux(void) { /* diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index b2015431e3..d1776522b7 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -24,15 +24,27 @@ */ #include #include +#include #include +#include +#include #include #include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; /* Define global data structure pointer to it*/ static gd_t gdata __attribute__ ((section(".data"))); static bd_t bdata __attribute__ ((section(".data"))); +static const char *image_name; +static u8 image_os; +static u32 image_load_addr; +static u32 image_entry_point; +static u32 image_size; inline void hang(void) { @@ -53,10 +65,188 @@ void board_init_f(ulong dummy) relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + switch (omap_boot_device()) { + case BOOT_DEVICE_MMC1: + omap_mmc_init(0); + break; + case BOOT_DEVICE_MMC2: + omap_mmc_init(1); + break; + } + return 0; +} +#endif + +static void parse_image_header(const struct image_header *header) +{ + u32 header_size = sizeof(struct image_header); + + if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) { + image_size = __be32_to_cpu(header->ih_size) + header_size; + image_entry_point = __be32_to_cpu(header->ih_load); + /* Load including the header */ + image_load_addr = image_entry_point - header_size; + image_os = header->ih_os; + image_name = (const char *)&header->ih_name; + debug("spl: payload image: %s load addr: 0x%x size: %d\n", + image_name, image_load_addr, image_size); + } else { + /* Signature not found - assume u-boot.bin */ + printf("mkimage signature not found - ih_magic = %x\n", + header->ih_magic); + puts("Assuming u-boot.bin ..\n"); + /* Let's assume U-Boot will not be more than 200 KB */ + image_size = 200 * 1024; + image_entry_point = CONFIG_SYS_TEXT_BASE; + image_load_addr = CONFIG_SYS_TEXT_BASE; + image_os = IH_OS_U_BOOT; + image_name = "U-Boot"; + } +} + +static void mmc_load_image_raw(struct mmc *mmc) +{ + u32 image_size_sectors, err; + const struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + err = mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1, + (void *)header); + + if (err <= 0) + goto end; + + parse_image_header(header); + + /* convert size to sectors - round up */ + image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) / + MMCSD_SECTOR_SIZE; + + /* Read the header too to avoid extra memcpy */ + err = mmc->block_dev.block_read(0, + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, + image_size_sectors, (void *)image_load_addr); + +end: + if (err <= 0) { + printf("spl: mmc blk read err - %d\n", err); + hang(); + } +} + +static void mmc_load_image_fat(struct mmc *mmc) +{ + s32 err; + struct image_header *header; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + err = fat_register_device(&mmc->block_dev, + CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION); + if (err) { + printf("spl: fat register err - %d\n", err); + hang(); + } + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + (u8 *)header, sizeof(struct image_header)); + if (err <= 0) + goto end; + + parse_image_header(header); + + err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, + (u8 *)image_load_addr, 0); + +end: + if (err <= 0) { + printf("spl: error reading image %s, err - %d\n", + CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err); + hang(); + } +} + +static void mmc_load_image(void) +{ + struct mmc *mmc; + int err; + u32 boot_mode; + + mmc_initialize(gd->bd); + /* We register only one device. So, the dev id is always 0 */ + mmc = find_mmc_device(0); + if (!mmc) { + puts("spl: mmc device not found!!\n"); + hang(); + } + + err = mmc_init(mmc); + if (err) { + printf("spl: mmc init failed: err - %d\n", err); + hang(); + } + + boot_mode = omap_boot_mode(); + if (boot_mode == MMCSD_MODE_RAW) { + debug("boot mode - RAW\n"); + mmc_load_image_raw(mmc); + } else if (boot_mode == MMCSD_MODE_FAT) { + debug("boot mode - FAT\n"); + mmc_load_image_fat(mmc); + } else { + puts("spl: wrong MMC boot mode\n"); + hang(); + } +} + +void jump_to_image_no_args(void) +{ + typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn)); + image_entry_noargs_t image_entry = + (image_entry_noargs_t) image_entry_point; + + image_entry(); +} + +void jump_to_image_no_args(void) __attribute__ ((noreturn)); void board_init_r(gd_t *id, ulong dummy) { - for (;;) - ; + u32 boot_device; + debug(">>spl:board_init_r()\n"); + + timer_init(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + boot_device = omap_boot_device(); + debug("boot device - %d\n", boot_device); + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + mmc_load_image(); + break; + default: + printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); + hang(); + break; + } + + switch (image_os) { + case IH_OS_U_BOOT: + debug("Jumping to U-Boot\n"); + jump_to_image_no_args(); + break; + default: + puts("Unsupported OS image.. Jumping nevertheless..\n"); + jump_to_image_no_args(); + } } void preloader_console_init(void) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 54dd509194..2e5739a1dd 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -39,6 +39,27 @@ DECLARE_GLOBAL_DATA_PTR; u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; +#ifdef CONFIG_SPL_BUILD +/* + * We use static variables because global data is not ready yet. + * Initialized data is available in SPL right from the beginning. + * We would not typically need to save these parameters in regular + * U-Boot. This is needed only in SPL at the moment. + */ +u32 omap4_boot_device = BOOT_DEVICE_MMC1; +u32 omap4_boot_mode = MMCSD_MODE_FAT; + +u32 omap_boot_device(void) +{ + return omap4_boot_device; +} + +u32 omap_boot_mode(void) +{ + return omap4_boot_mode; +} +#endif + void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) { int i; diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S index 6abfbbaa13..91525ecd46 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S @@ -27,6 +27,37 @@ */ #include +#ifdef CONFIG_SPL_BUILD +.global save_boot_params +save_boot_params: + /* + * See if the rom code passed pointer is valid: + * It is not valid if it is not in non-secure SRAM + * This may happen if you are booting with the help of + * debugger + */ + ldr r2, =NON_SECURE_SRAM_START + cmp r2, r0 + bgt 1f + ldr r2, =NON_SECURE_SRAM_END + cmp r2, r0 + blt 1f + + /* Store the boot device in omap4_boot_device */ + ldr r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device + and r2, #BOOT_DEVICE_MASK + ldr r3, =omap4_boot_device + str r2, [r3] @ omap4_boot_device <- r1 + + /* Store the boot mode (raw/FAT) in omap4_boot_mode */ + ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr + ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr + ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode + ldr r3, =omap4_boot_mode + str r2, [r3] +1: + bx lr +#endif .globl lowlevel_init lowlevel_init: diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 02a25354e9..db8e9d2f18 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -134,6 +134,7 @@ IRQ_STACK_START_IN: */ reset: + bl save_boot_params /* * set the cpu to SVC32 mode */ diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index a8dbedb45d..563544fb01 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -144,4 +144,12 @@ struct s32ktimer { #define OMAP4430_ES2_2 0x44300220 #define OMAP4430_ES2_3 0x44300230 +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 + #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 69d53d2c72..d3cb857282 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -36,4 +36,21 @@ void preloader_console_init(void); +/* Boot device */ +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 + +/* Boot type */ +#define MMCSD_MODE_UNDEFINED 0 +#define MMCSD_MODE_RAW 1 +#define MMCSD_MODE_FAT 2 + +u32 omap_boot_device(void); +u32 omap_boot_mode(void); + #endif /* _OMAP_COMMON_H_ */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 1112362b32..f6f283a735 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -252,6 +252,11 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 6a6be9e9b8..346763d722 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -258,6 +258,11 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -- cgit v1.2.3