From 0c00d03aca356c295daafe82873ecfc9d7769dd9 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:41 +0800 Subject: driver: misc: Add MU and S400 API to communicate with Sentinel Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx8ulp/s400_api.h | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8ulp/s400_api.h (limited to 'arch/arm/include/asm/arch-imx8ulp/s400_api.h') diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h new file mode 100644 index 0000000000..3ba6b525c5 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __S400_API_H__ +#define __S400_API_H__ + +#define AHAB_VERSION 0x6 +#define AHAB_CMD_TAG 0x17 +#define AHAB_RESP_TAG 0xe1 + +#define AHAB_LOG_CID 0x21 +#define AHAB_AUTH_OEM_CTNR_CID 0x87 +#define AHAB_VERIFY_IMG_CID 0x88 +#define AHAB_RELEASE_CTNR_CID 0x89 +#define AHAB_RELEASE_RDC_REQ_CID 0xC4 + +#define S400_MAX_MSG 8U + +struct imx8ulp_s400_msg { + u8 version; + u8 size; + u8 command; + u8 tag; + u32 data[(S400_MAX_MSG - 1U)]; +}; + +int ahab_release_rdc(u8 core_id); +#endif -- cgit v1.2.3 From 6306f75d8e498babd7754c1414fc342b0d198b71 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:52 +0800 Subject: drivers: misc: imx8ulp: Add S400 API for image authentication Add S400 API for image authentication Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/s400_api.h | 8 +- drivers/misc/imx8ulp/s400_api.c | 121 ++++++++++++++++++++++++++- 2 files changed, 127 insertions(+), 2 deletions(-) (limited to 'arch/arm/include/asm/arch-imx8ulp/s400_api.h') diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h index 3ba6b525c5..30dab8be24 100644 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -15,6 +15,7 @@ #define AHAB_VERIFY_IMG_CID 0x88 #define AHAB_RELEASE_CTNR_CID 0x89 #define AHAB_RELEASE_RDC_REQ_CID 0xC4 +#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 #define S400_MAX_MSG 8U @@ -26,5 +27,10 @@ struct imx8ulp_s400_msg { u32 data[(S400_MAX_MSG - 1U)]; }; -int ahab_release_rdc(u8 core_id); +int ahab_release_rdc(u8 core_id, u32 *response); +int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); +int ahab_release_container(u32 *response); +int ahab_verify_image(u32 img_id, u32 *response); +int ahab_forward_lifecycle(u16 life_cycle, u32 *response); + #endif diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c index 82fd3117a4..4047d6efee 100644 --- a/drivers/misc/imx8ulp/s400_api.c +++ b/drivers/misc/imx8ulp/s400_api.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -int ahab_release_rdc(u8 core_id) +int ahab_release_rdc(u8 core_id, u32 *response) { struct udevice *dev = gd->arch.s400_dev; int size = sizeof(struct imx8ulp_s400_msg); @@ -37,5 +37,124 @@ int ahab_release_rdc(u8 core_id) printf("Error: %s: ret %d, core id %u, response 0x%x\n", __func__, ret, core_id, msg.data[0]); + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = AHAB_AUTH_OEM_CTNR_CID; + msg.data[0] = upper_32_bits(ctnr_addr); + msg.data[1] = lower_32_bits(ctnr_addr); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n", + __func__, ret, ctnr_addr, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_release_container(u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 1; + msg.command = AHAB_RELEASE_CTNR_CID; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_verify_image(u32 img_id, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = AHAB_VERIFY_IMG_CID; + msg.data[0] = 1 << img_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, img_id %u, response 0x%x\n", + __func__, ret, img_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} + +int ahab_forward_lifecycle(u16 life_cycle, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID; + msg.data[0] = life_cycle; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n", + __func__, ret, life_cycle, msg.data[0]); + + if (response) + *response = msg.data[0]; + return ret; } -- cgit v1.2.3 From 7aeaf4d9a687bcc2b98f3305f2d4e792a9004f70 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:53 +0800 Subject: drivers: misc: imx8ulp: Update S400 API for release RDC The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx8ulp/s400_api.h | 2 +- drivers/misc/imx8ulp/s400_api.c | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm/arch-imx8ulp/s400_api.h') diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h index 30dab8be24..41ad4002b1 100644 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -27,7 +27,7 @@ struct imx8ulp_s400_msg { u32 data[(S400_MAX_MSG - 1U)]; }; -int ahab_release_rdc(u8 core_id, u32 *response); +int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response); int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ahab_release_container(u32 *response); int ahab_verify_image(u32 img_id, u32 *response); diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c index 4047d6efee..315221a463 100644 --- a/drivers/misc/imx8ulp/s400_api.c +++ b/drivers/misc/imx8ulp/s400_api.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -int ahab_release_rdc(u8 core_id, u32 *response) +int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response) { struct udevice *dev = gd->arch.s400_dev; int size = sizeof(struct imx8ulp_s400_msg); @@ -30,7 +30,10 @@ int ahab_release_rdc(u8 core_id, u32 *response) msg.tag = AHAB_CMD_TAG; msg.size = 2; msg.command = AHAB_RELEASE_RDC_REQ_CID; - msg.data[0] = core_id; + if (xrdc) + msg.data[0] = (0x78 << 8) | core_id; + else + msg.data[0] = (0x74 << 8) | core_id; ret = misc_call(dev, false, &msg, size, &msg, size); if (ret) -- cgit v1.2.3 From 26b53212b8f207243e5621d6e121bac559c59678 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sat, 7 Aug 2021 16:00:54 +0800 Subject: drivers: misc: s400_api: Update API for fuse read and write Add API to support fuse read and write Signed-off-by: Ye Li --- arch/arm/include/asm/arch-imx8ulp/s400_api.h | 7 ++- drivers/misc/imx8ulp/s400_api.c | 81 ++++++++++++++++++++++++++++ 2 files changed, 87 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/arch-imx8ulp/s400_api.h') diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h index 41ad4002b1..c848f0dfb8 100644 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -14,8 +14,11 @@ #define AHAB_AUTH_OEM_CTNR_CID 0x87 #define AHAB_VERIFY_IMG_CID 0x88 #define AHAB_RELEASE_CTNR_CID 0x89 -#define AHAB_RELEASE_RDC_REQ_CID 0xC4 +#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 #define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 +#define AHAB_READ_FUSE_REQ_CID 0x97 +#define AHAB_RELEASE_RDC_REQ_CID 0xC4 +#define AHAB_WRITE_FUSE_REQ_CID 0xD6 #define S400_MAX_MSG 8U @@ -32,5 +35,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ahab_release_container(u32 *response); int ahab_verify_image(u32 img_id, u32 *response); int ahab_forward_lifecycle(u16 life_cycle, u32 *response); +int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); +int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); #endif diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c index 315221a463..d76a95febe 100644 --- a/drivers/misc/imx8ulp/s400_api.c +++ b/drivers/misc/imx8ulp/s400_api.c @@ -161,3 +161,84 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response) return ret; } + +int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + if (!fuse_words) { + printf("Invalid parameters for fuse read\n"); + return -EINVAL; + } + + if ((fuse_id != 1 && fuse_num != 1) || + (fuse_id == 1 && fuse_num != 4)) { + printf("Invalid fuse number parameter\n"); + return -EINVAL; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = AHAB_READ_FUSE_REQ_CID; + msg.data[0] = fuse_id; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + fuse_words[0] = msg.data[1]; + if (fuse_id == 1) { + /* OTP_UNIQ_ID */ + fuse_words[1] = msg.data[2]; + fuse_words[2] = msg.data[3]; + fuse_words[3] = msg.data[4]; + } + + return ret; +} + +int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct imx8ulp_s400_msg); + struct imx8ulp_s400_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = AHAB_WRITE_FUSE_REQ_CID; + msg.data[0] = (32 << 16) | (fuse_id << 5); + if (lock) + msg.data[0] |= (1 << 31); + + msg.data[1] = fuse_val; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n", + __func__, ret, fuse_id, msg.data[0]); + + if (response) + *response = msg.data[0]; + + return ret; +} -- cgit v1.2.3