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path: root/drivers/timer/tsc_timer.c
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* efi: Use a fixed value for the timer clockSimon Glass2023-03-131-0/+9
| | | | | | | | It is not yet clear how to read the timer via EFI. The current value seems much too high on a Framework laptop I tried. Adjust it to a lower hard-coded value for now. Signed-off-by: Simon Glass <sjg@chromium.org>
* treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass2021-09-251-1/+1
| | | | | | | Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQBin Meng2021-08-021-2/+3
| | | | | | | | | | | | | Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: tsc_timer: Correct overflow in __udelay()Simon Glass2021-02-011-1/+1
| | | | | | | | | | At present long delays such as msleep(2000) can cause an overflow in this function. There is no need for this, since it already uses a 64-bit int. Add a cast to correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Reduce size for TPLSimon Glass2021-01-051-1/+3
| | | | | | | | | | Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-051-2/+2
| | | | | | | | | | | | At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: Return count from timer_ops.get_countSean Anderson2020-10-221-4/+2
| | | | | | | | | No timer drivers return an error from get_count. Instead of possibly returning an error, just return the count directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop bootstage.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: timer: Reduce timer code size in TPL on Intel CPUsSimon Glass2019-12-151-2/+5
| | | | | | | | | | | | | | | Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: use a timer base of 0Simon Glass2019-12-151-1/+2
| | | | | | | | | | | | | | | | On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* common: Move get_ticks() function out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: timer: Use a separate flag for whether timer is initedSimon Glass2019-11-031-1/+2
| | | | | | | | | | | | | | At present the value of the timer base is used to determine whether the timer has been set up or not. It is true that the timer is essentially never exactly 0 when it is read. However 'time 0' may indicate the time that the machine was reset so it is useful to be able to denote that. Update the code to use a separate flag instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: Set up the timer in timer_early_get_count()Simon Glass2019-11-031-0/+2
| | | | | | | | | | This function can be called before the timer is set up. Make sure that the init function is called so that it works correctly. This is needed so that bootstage can work correctly in TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: tsc: Add support for native calibration of TSC freqBernhard Messerklinger2019-02-121-0/+55
| | | | | | | | | | | Add native tsc calibration function. Calibrate the tsc timer the same way as linux does in arch/x86/kernel/tsc.c. Fixes booting for Apollo Lake processors. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng2018-11-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Introduce config option for early timer frequencyBin Meng2018-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Try hardware calibration firstBin Meng2018-08-201-11/+16
| | | | | | | | | | | | | At present if TSC frequency is provided in the device tree, it takes precedence over hardware calibration result. This swaps the order to try hardware calibration first and uses device tree as last resort. This can be helpful when a generic dts (eg: coreboot/efi payload) is supposed to work on as many hardware as possible, including emulators like QEMU where TSC hardware calibration sometimes fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* x86: timer: tsc: Allow specifying clock rate from device tree againBin Meng2018-07-021-2/+11
| | | | | | | | | | | | | | With the introduction of early timer support in the TSC driver, the capability of getting clock rate from device tree was lost unfortunately. Now we bring such functionality back, but with a limitation that when TSC is used as early timer, specifying clock rate from device tree does not work. This fixes random boot failures seen on QEMU targets: printing "TSC frequency is ZERO" and reset forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: add support for reading CPU freq from cpuidChristian Gmeiner2018-06-131-5/+24
| | | | | | | | | | | | Starting with cpuid level 0x16 (Skylake-based processors) it is possible to get CPU base freq via cpuid. This fixes booting on a skylake based system. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed wrong indention of labels] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: x86: Allow TSC timer to be used before DM is readySimon Glass2017-09-161-5/+25
| | | | | | | | | | | With bootstage we need access to the timer before driver model is set up. To handle this, put the required state in global_data and provide a new function to set up the device, separate from the driver's probe() method. This will be used by the 'early' timer also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: tsc: Add Airmont reference clock valuesBin Meng2017-09-161-7/+10
| | | | | | | | | | | | Per the Intel 64 and IA-32 Architecture Software Developer's Manual, add the reference clock for Intel Atom Processors based on the Airmont Microarchitecture (Braswell). This keeps in sync with Linux kernel commit: 6fcb41c: x86/tsc_msr: Add Airmont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()Bin Meng2017-08-011-4/+9
| | | | | | | | | | | Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr(), as that better describes what the routine does. This keeps in sync with Linux kernel commit: 02c0cd2: x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Correct Silvermont reference clock valuesBin Meng2017-08-011-4/+4
| | | | | | | | | | | | | | | | | | | | Atom processors use a 19.2 MHz crystal oscillator. Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz. Later processors generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz. Update the Silvermont-based tables accordingly, matching the Software Developers Manual. Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry for VLV2. This keeps in sync with Linux kernel commit: 05680e7: x86/tsc_msr: Correct Silvermont reference clock values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Update comments and expand definitions in freq_desc_tables[]Bin Meng2017-08-011-15/+9
| | | | | | | | | | | | Some processor abbreviations in the comments of freq_desc_tables[] are obscure. This updates part of these to mention processors that are known to us. Also expand frequency definitions. This keeps in sync with Linux kernel commit: 9e0cae9: x86/tsc_msr: Update comments, expand definitions Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()Bin Meng2017-08-011-9/+0
| | | | | | | | | | | If either ratio or freq is zero, the return value is zero. There is no need to create a fail branch and return zero there. This keeps in sync with Linux kernel commit: 14bb4e3: x86/tsc_msr: Remove debugging messages Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Identify Intel-specific codeBin Meng2017-08-011-0/+4
| | | | | | | | | | | try_msr_calibrate_tsc() is currently Intel-specific, and should not execute on any other vendor's parts. This keeps in sync with Linux kernel commit: ba82683: x86/tsc_msr: Identify Intel-specific code Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Read all ratio bits from MSR_PLATFORM_INFOBin Meng2017-08-011-1/+1
| | | | | | | | | | | | | | | | | Currently we read the tsc radio like this: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f; Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the Intel manual, the ratio bits are bit 8-15. Fix this problem by masking 0xff instead. This keeps in sync with Linux kernel commit: 886123f: x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Move i8254_init() to x86_cpu_init_f()Bin Meng2015-12-091-10/+0
| | | | | | | | | | | Right now i8254_init() is called from timer_init() in the tsc timer driver. But actually i8254 and tsc are completely different things. Since tsc timer has been converted to driver model, we should find a new place that is appropriate for U-Boot to call i8254_init(), which is now x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-011-0/+389
To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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