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* fpga: Add a FPGA_STRATIX_II optionSimon Glass2023-02-071-0/+6
| | | | | | | There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org>
* fpga: Add a LATTICE optionSimon Glass2023-02-071-0/+6
| | | | | | | There is no Kconfig option for this code, but it seems to be useful. Add one. Signed-off-by: Simon Glass <sjg@chromium.org>
* global: Finish CONFIG -> CFG migrationTom Rini2023-01-202-7/+7
| | | | | | | | | | | | | At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fpga: Migrate CONFIG_MAX_FPGA_DEVICES to KconfigTom Rini2023-01-202-5/+5
| | | | | | | | This is always defined to 5, so use that as the default. Cc: Michal Simek <michal.simek@amd.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@amd.com>
* misc: fs_loader: Add function to get the chosen loaderSean Anderson2023-01-121-25/+3
| | | | | | | | | | | | | | The fs_loader device is used to pull in settings via the chosen node. However, there was no library function for this, so arria10 was doing it explicitly. This function subsumes that, and uses ofnode_get_chosen_node instead of navigating the device tree directly. Because fs_loader pulls its config from the environment by default, it's fine to create a device with nothing backing it at all. Doing this allows enabling CONFIG_FS_LOADER without needing to modify the device tree. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* global: Migrate CONFIG_FPGA_DELAY to CFGTom Rini2022-12-235-71/+71
| | | | | | Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_FPGA_CHECK_BUSY to KconfigTom Rini2022-12-234-9/+6
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini <trini@konsulko.com>
* global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini2022-12-056-43/+43
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fpga: virtex2: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-39/+30
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-11-ada@thorsis.com
* fpga: spartan3: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-43/+37
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-10-ada@thorsis.com
* fpga: spartan2: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-43/+37
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-9-ada@thorsis.com
* fpga: ACEX1K: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-21/+16
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-8-ada@thorsis.com
* fpga: cyclon2: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-22/+16
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-7-ada@thorsis.com
* fpga: altera: Use logging feature instead of FPGA_DEBUGAlexander Dahl2022-10-101-7/+4
| | | | | | | | | Instead of using DEBUG or LOG_DEBUG the driver still had its own definition for debug output. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-6-ada@thorsis.com
* fpga: virtex2: Fix printf format string warningsAlexander Dahl2022-10-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Warning appears if built with FPGA_DEBUG defined: CC drivers/fpga/virtex2.o /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ssm_load’: /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:333:11: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=] PRINTF("%s:%d:done went active early, bytecount = %d\n", ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __func__, __LINE__, bytecount); ~~~~~~~~~ /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’ #define PRINTF(fmt, args...) printf(fmt, ##args) ^~~ /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c: In function ‘virtex2_ss_load’: /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:468:12: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=] PRINTF("%s:%d:done went active early, bytecount = %d\n", ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __func__, __LINE__, bytecount); ~~~~~~~~~ /mnt/data/adahl/src/u-boot/drivers/fpga/virtex2.c:25:37: note: in definition of macro ‘PRINTF’ #define PRINTF(fmt, args...) printf(fmt, ##args) ^~~ Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-5-ada@thorsis.com
* fpga: spartan3: Fix printf arguments warningAlexander Dahl2022-10-101-1/+1
| | | | | | | | | | | | | | | | | | | The additional comma messes up the arguments. Warning appears if built with FPGA_DEBUG defined: CC drivers/fpga/spartan3.o /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’: /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:118:11: warning: too many arguments for format [-Wformat-extra-args] PRINTF ("%s: Function Table:\n" ^~~~~~~~~~~~~~~~~~~~~~~ /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:18:37: note: in definition of macro ‘PRINTF’ #define PRINTF(fmt,args...) printf (fmt ,##args) ^~~ Fixes: 875c78934ee2 ("Add Xilinx Spartan3 family FPGA support Patch by Kurt Stremerch, 14 February 2005") Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-4-ada@thorsis.com
* fpga: spartan2: Fix printf arguments warningAlexander Dahl2022-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | That extra comma messes up format arguments. Warning appears if built with FPGA_DEBUG defined: CC drivers/fpga/spartan2.o /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c: In function ‘spartan2_sp_load’: /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:112:11: warning: too many arguments for format [-Wformat-extra-args] PRINTF ("%s: Function Table:\n" ^~~~~~~~~~~~~~~~~~~~~~~ /mnt/data/adahl/src/u-boot/drivers/fpga/spartan2.c:12:37: note: in definition of macro ‘PRINTF’ #define PRINTF(fmt,args...) printf (fmt ,##args) ^~~ CC drivers/fpga/spartan3.o /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c: In function ‘spartan3_sp_load’: /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:117:11: warning: too many arguments for format [-Wformat-extra-args] PRINTF ("%s: Function Table:\n" ^~~~~~~~~~~~~~~~~~~~~~~ /mnt/data/adahl/src/u-boot/drivers/fpga/spartan3.c:17:37: note: in definition of macro ‘PRINTF’ #define PRINTF(fmt,args...) printf (fmt ,##args) ^~~ Fixes: e221174377d7 ("Initial revision") Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-3-ada@thorsis.com
* fpga: Add missing Kconfig symbols for old FPGA driversAlexander Dahl2022-10-101-0/+12
| | | | | | | | Those drivers could not be built anymore without those options present. Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221007122003.11239-2-ada@thorsis.com
* dm: fpga: Introduce new uclassAlexander Dahl2022-10-054-0/+50
| | | | | | | | | | | | For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com>
* treewide: Drop image_header_t typedefSimon Glass2022-09-291-2/+2
| | | | | | | This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
* cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese2022-09-182-8/+8
| | | | | | | | | | Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
* fpga: zynq: Remove post config info message for SPLStefan Herbrechtsmeier2022-09-121-1/+2
| | | | | | | | | | | | The drivers informs the user that a post config was not run after FPGA configuration. This message is unnecessary in SPL because the ps7_post_config function is called via spl_board_prepare_for_boot function before jump_to_image_no_args function from board_init_r function. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: zynqmp: support loading encrypted bitfilesAdrian Fiergolski2022-07-261-0/+8
| | | | | | | | | | | | | | | | | | Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle loading encrypted bitfiles. This feature requires encrypted FSBL, as according to UG1085: "The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs, as a key source to the AES engine if the FSBL is not encrypted. This prevents using the BBRAM or eFUSE as the key source to the AES engine during run-time applications." Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: zynqmp: support loading authenticated imagesOleksandr Suvorov2022-07-261-5/+28
| | | | | | | | | | | | Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to handle loading authenticated images (DDR). Based on solution by Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Link: https://lore.kernel.org/r/20220722141614.297383-13-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: zynqmp: add bitstream compatible checkingOleksandr Suvorov2022-07-261-0/+34
| | | | | | | | | | | Check whether the FPGA ZynqMP driver supports the given bitstream image type. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-12-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: zynqmp: reduce zynqmppl_load() codeOleksandr Suvorov2022-07-261-11/+6
| | | | | | | | | | | | | Reduce the function code by calling xilinx_pm_request() once only. Use the same variable bsize_req to store either bstream size in bytes or an address of bstream size according to a type required by the firmware version. Remove obsolete debug(). Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-11-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: xilinx: pass compatible flags to load() callbackOleksandr Suvorov2022-07-267-7/+7
| | | | | | | | | | | These flags may be used to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: add fpga_compatible2flagOleksandr Suvorov2022-07-261-0/+26
| | | | | | | | | | | Add a "compatible" string to binary flag converter, which uses a callback str2flag() of given FPGA driver if available. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-8-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: pass compatible flags to fpga_load()Oleksandr Suvorov2022-07-262-3/+4
| | | | | | | | | | | These flags may be used to check whether an FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-7-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: xilinx: pass compatible flags to xilinx_load()Oleksandr Suvorov2022-07-262-2/+2
| | | | | | | | | | | This flag is used to check whether a Xilinx FPGA driver is able to load a particular FPGA bitstream image. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-6-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: zynqmp: add str2flags callOleksandr Suvorov2022-07-261-1/+10
| | | | | | | | | | Add a call to convert FPGA "compatible" string to a binary flag. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-5-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: add option for loading FPGA secure bitstreamsOleksandr Suvorov2022-07-264-4/+18
| | | | | | | | | | | | | It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Tested-by: Ricardo Salveti <ricardo@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: Convert SYS_FPGA_PROG_FEEDBACK to KconfigAlexander Dahl2022-07-263-5/+7
| | | | | | | | This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* fpga: Convert SYS_FPGA_CHECK_CTRLC to KconfigAlexander Dahl2022-07-262-7/+6
| | | | | | | | | | After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the whitelist") downstream builds failed for boards setting this in include/configs/… Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* Merge branch 'next'Tom Rini2022-07-111-0/+6
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| * Convert CONFIG_FPGA_STRATIX_V to KconfigTom Rini2022-06-281-0/+6
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_FPGA_STRATIX_V Signed-off-by: Tom Rini <trini@konsulko.com>
* | socfpga: arria10: Wait for fifo empty after writing bitstreamPaweł Anikiel2022-07-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | For some reason, on the Mercury+ AA1 module, calling fpgamgr_wait_early_user_mode immediately after writing the peripheral bitstream leaves the fpga in a broken state (ddr calibration hangs). Adding a delay before the first sync word is written seems to fix this. Inspecting the fpgamgr registers before and after the delay, imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit (instead of a hardcoded delay) also fixes the issue. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | socfpga: arria10: Improve bitstream loading speedPaweł Anikiel2022-07-011-2/+18
|/ | | | | | | | | | | | | | | | | | Apply some optimizations to speed up bitstream loading (both for full and split periph/core bitstreams): * Change the size of the first fs read, so that all the subsequent reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE). This value was chosen so that in subsequent reads the fat fs driver doesn't have to allocate a temporary buffer in get_contents (assuming 8KiB clusters). * Change the buffer size to a larger value when reading to ddr (but not too large, because large transfers cause a stack overflow in the dwmmc driver). Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee2021-12-171-1/+2
| | | | | | | | | Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
* WS cleanup: remove trailing empty linesWolfgang Denk2021-09-301-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-081-1/+1
| | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini2021-02-231-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
| * fpga: zynqpl: fix buffer alignmentMichael Walle2021-02-231-1/+1
| | | | | | | | | | | | | | | | | | Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is subtracted. It seems that the original intention was to just subtract ARCH_DMA_MINALIGN. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | image: Adjust the workings of fit_check_format()Simon Glass2021-02-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this function does not accept a size for the FIT. This means that it must be read from the FIT itself, introducing potential security risk. Update the function to include a size parameter, which can be invalid, in which case fit_check_format() calculates it. For now no callers pass the size, but this can be updated later. Also adjust the return value to an error code so that all the different types of problems can be distinguished by the user. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Bruce Monroe <bruce.monroe@intel.com> Reported-by: Arie Haenel <arie.haenel@intel.com> Reported-by: Julien Lenoir <julien.lenoir@intel.com>
* | common: Drop asm/global_data.h from common headerSimon Glass2021-02-022-0/+2
|/ | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: socfpga: soc64: Add ATF support for FPGA reconfig driverChee Hong Ang2021-01-151-0/+139
| | | | | | | In non-secure mode (EL2), FPGA reconfiguration driver calls the SMC/PSCI services provided by ATF to configure the FPGA. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
* arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-1/+1
| | | | | | | | Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang2020-10-091-0/+3
| | | | | | | | Ensure watchdog reset is not triggered if the fpga reconfiguration is taking too long. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-094-11/+12
| | | | | | | | | Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* fpga: zynqmp: Protect zynqmp_loads() for SPLMichal Simek2020-09-231-1/+1
| | | | | | | if conditions should match. Fixes: a18d09ea384f ("fpga: zynqmp: Add secure bitstream loading for ZynqMP") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-14 03:23:36 +0000