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* ddr: altera: Clean up scc_mgr_set_hhp_extras()Marek Vasut2015-08-081-15/+22
| | | | | | | | Minor coding style cleanup for this function. Furthermore, move ad-hoc debug_cond() calls from the only location from where this function is invoked into this actual function. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_*_delay() argsMarek Vasut2015-08-081-18/+14
| | | | | | | Zap args which are not used by these functions, in particular the write_group is often passed, but unused. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()Marek Vasut2015-08-081-9/+12
| | | | | | | Remove unused write_group and group_bgn argument from this function. Document the function using kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_set_oct_out1_delay()Marek Vasut2015-08-081-9/+14
| | | | | | Make this function more readable, no functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_set_bypass_mode()Marek Vasut2015-08-081-11/+14
| | | | | | The mode argument of this function is not used at all, zap it. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()Marek Vasut2015-08-081-11/+15
| | | | | | | Make this function more readable, no functional change. Also, zap the forward declaration, which is no longer needed. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Implement universal scc_mgr_set_all_ranks()Marek Vasut2015-08-081-53/+42
| | | | | | | | Implement universal scc_mgr_set_all_ranks() function and convert various ad-hoc implementations of similar functionality to use this single function. Document the function in kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Shuffle around scc_mgr_set_*all_ranks()Marek Vasut2015-08-081-11/+8
| | | | | | Shuffle the code around a bit, but without any functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_initialize()Marek Vasut2015-08-081-4/+10
| | | | | | Clean up the comments and add kerneldoc. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Implement universal scc manager config functionMarek Vasut2015-08-081-40/+29
| | | | | | | Implement unified scc_mgr_set() function and convert all those 9 scc_mgr_set_*() ad-hoc functions to call this one function. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Reorder scc manager functionsMarek Vasut2015-08-081-100/+95
| | | | | | | This patch just puts functions which look similar next to each other, so they can be sorted out. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc manager function argsMarek Vasut2015-08-081-17/+13
| | | | | | | Clean up the unused args of the functions used to configure the SCC manager. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up reg_file_set*()Marek Vasut2015-08-081-36/+7
| | | | | | | Turn the insides of these functions into trivial clrsetbits_le32() and fix the data type of their argument to reflect it's actual size. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up initialize_hps_phy()Marek Vasut2015-08-081-0/+5
| | | | | | Add brief kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up initialize_reg_file()Marek Vasut2015-08-081-0/+5
| | | | | | Add brief kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up hc_initialize_rom_data()Marek Vasut2015-08-081-10/+10
| | | | | | Clean the function up, fix data types, add kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Massage addr into I/O accessorsMarek Vasut2015-08-081-424/+248
| | | | | | | | Get rid of invocations of this sort: addr = (u32)&base->reg; writel(val, addr); Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directlyMarek Vasut2015-08-082-15/+9
| | | | | | | Use the proper structure which describes these registers, especially since this is already in place. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESSMarek Vasut2015-08-083-235/+235
| | | | | | | Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS in the code. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Pluck out remaining sdr_get_addr() callsMarek Vasut2015-08-082-119/+75
| | | | | | | Remove the remaining invocations of sdr_get_addr() and the function itself. This makes the code a bit less cryptic. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)Marek Vasut2015-08-081-26/+26
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)Marek Vasut2015-08-081-63/+63
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)Marek Vasut2015-08-081-45/+45
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)Marek Vasut2015-08-081-22/+24
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"Marek Vasut2015-08-081-3/+3
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up ugly casts in sdram_calibration_full()Marek Vasut2015-08-081-29/+21
| | | | | | | Use the correct formating string in those debug_cond() invocations and zap those unnecessary ugly casts. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Minor indent fix in set_rank_and_odt_mask()Marek Vasut2015-08-081-1/+1
| | | | | | | Fix the position of the } else { statement to make it correctly indented. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Fix debug message format in sequencerMarek Vasut2015-08-081-7/+7
| | | | | | | | | | The debug messages missed proper newlines and/or spaces in them. Fix the formatting. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@konsulko.com>
* ddr: altera: Fix typo in mp_threshold1 programmingMarek Vasut2015-08-081-1/+1
| | | | | | | | | | | It is the configuration data that should go into the register, not the register mask, just like the surrounding code does it. Fix this typo. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@konsulko.com>
* ddr: altera: Move struct sdram_prot_rule prototypeMarek Vasut2015-08-081-0/+13
| | | | | | | | | | | Move the structure prototype from sdram.h header file into sdram.c source file, since it is used only there and for local purpose only. There is no point in having it global. While at this move, fix the data types in the structure from uintNN_t to uNN and fix the coding style a bit. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move sdram_config.h to board dirMarek Vasut2015-08-081-1/+6
| | | | | | | This file is absolutelly positively board specific, so move it into the correct place. Signed-off-by: Marek Vasut <marex@denx.de>
* driver/ddr/altera: Add the sdram calibration portionDinh Nguyen2015-08-087-0/+4985
| | | | | | This patch adds the DDR calibration portion of the Altera SDRAM driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* driver/ddr/altera: Add DDR driver for Altera's SDRAM controllerDinh Nguyen2015-08-081-0/+799
| | | | | | | | This patch enables the SDRAM controller that is used on Altera's SoCFPGA family. This patch configures the SDRAM controller based on a configuration file that is generated from the Quartus tool, sdram_config.h. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* drivers/ddr/fsl: Adjust bstopre valueYork Sun2015-08-032-5/+7
| | | | | | | | | By default the bstopre value has been set to 0x100, used to be 1/4 value of refint. Modern DDR has increased the refresh time. Adjust to 1/4 of refresh interval dynamically. Individual board can still override this value in board ddr file, or to use auto-precharge. Signed-off-by: York Sun <yorksun@freescale.com>
* arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese2015-07-231-5/+0
| | | | | | | Remove the incorrect PEX macros from the DDR header. And insert the correct ones in ctrl_pex.h instead. Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdrStefan Roese2015-07-2343-0/+17368
| | | | | | | | | | | | | | | | | | This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese2015-07-2321-0/+0
| | | | | | | | | | | | | | | | With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: Stefan Roese <sr@denx.de>
* driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-201-0/+8
| | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* arm: mvebu: db-mv784mp-gp: Fix ECC I2C addressStefan Roese2015-05-051-1/+1
| | | | | | | | The macro to select the I2C address for ECC bus-width detection was defined incorrectly for the Marvell DB-MV784MP-GP board. This patch changes the macro to the correct value to fix this issue. Signed-off-by: Stefan Roese <sr@denx.de>
* driver/ddr/fsl: Add workaround for DDR erratum A008511York Sun2015-04-231-1/+95
| | | | | | | | This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add built-in memory test for DDR4 driverYork Sun2015-04-231-0/+73
| | | | | | | | | Add built-in memory test to catch errors after DDR is initialized, before any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST. An environmental variable "ddr_bist" is checked before starting test. It takes a while (several seconds) depending on system memory size. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix driver to support empty first slotYork Sun2015-04-235-28/+56
| | | | | | | | CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Update DDR driver for DDR4York Sun2015-04-234-10/+88
| | | | | | | | | | Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>
* MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT registerCurt Brune2015-04-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the MPC8555/MPC8541 reference manual the SS_EN (source synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set during initialization. >From section 9.4.1.8 of that manual: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, "DDR SDRAM Initialization Sequence," details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. In addition, Freescale application note AN2805 is also very clear that this bit must be set. This patch reverts a change introduced by commit 457caecdbca3df21a93abff19eab12dbc61b7897. Testing Done: Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS and inspected the generated assembly code to verify the SS_EN bit was being set. There is one extra instruction emitted: fff9b774: 65 29 80 00 oris r9,r9,32768 Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no additional instructions were emitted related to this patch. Booted an image on a MPC8541 based board successfully. Signed-off-by: Curt Brune <curt@cumulusnetworks.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add sync of refreshYork Sun2015-02-242-0/+59
| | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-241-1/+1
| | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-2412-152/+180
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workround for erratumn A008514York Sun2015-02-241-5/+17
| | | | | | | Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add workaround for A008336York Sun2015-02-241-0/+22
| | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Adjust CAS to preamble override for emulatorYork Sun2015-02-241-1/+5
| | | | | | | | | On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun <yorksun@freescale.com>
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