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* ddr: fsl: Fix re-align of verbose DRAM information for non-SPL buildsPali Rohár2022-09-231-0/+3
| | | | | | | | During init_dram() is called also compute_lowest_common_dimm_parameters() function which prints multi-line detailed output. So print also re-aligning filler after "Detected ?DIMM" line to have "DRAM: " output aligned. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit modePali Rohár2022-09-231-4/+10
| | | | | | | | | | | U-Boot core code already handles the case when RAM size is bigger than CONFIG_MAX_MEM_MAPPED. So there is no need to do duplicate check in fsl ddr driver for CONFIG_MAX_MEM_MAPPED. Instead simplify code to just check if RAM size can be representable in phys_size_t type. And avoid printing warning if phys_size_t is just 1 byte smaller than RAM size, which is the typical situation with 4 GB DDR module. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_tPali Rohár2022-09-231-0/+4
| | | | | | | | | | | | | | | | | Function fsl_ddr_compute() always return size in unsigned long long type, but function fsl_ddr_sdram_size() returns size in phys_size_t type. When 36-bit addressing mode is not enabled then phys_size_t type is only 32-bit and thus it cannot store value 4GB (0x100000000). Function fsl_ddr_sdram_size() in this case returns truncated value 0x0. Fix this issue by returning the highest representable value, which is 0xffffffff (4GB - 1 byte). This change fixes crashing of proper U-Boot because it detected 4 GB module as RAM with zero size. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Fix checking for maximal mappable memoryPali Rohár2022-09-231-5/+14
| | | | | | | | | Check needs to be done against CONFIG_MAX_MEM_MAPPED macro and not fixed size 4GB (as CONFIG_MAX_MEM_MAPPED can be lower and for example for e500 cores it is just 2GB). Also fix printf re-align, which should be applied only for non-SPL builds, during init_dram() call. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Make bank_addr_bits reflect actual bitsSean Anderson2022-09-062-2/+2
| | | | | | | | | | | | | | | | | | | | In both the Freescale DDR controller and the SPD spec, bank address bits are stored as the number of bank address bits minus 2. For example, if a chip had 8 banks (3 total bank address bits), the value of bank_addr_bits would be 1. This is rather surprising for users configuring their memory manually, since they can't set bank_addr_bits to the actual number of bank address bits. Rectify this. There is at least one example of this kind of mistake already, in board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank address bits, but bank_addr_bits was set to 2, implying 4 bank address bits. Such a value is reserved in BA_BITS_CS, but I suspect the controller simply ignores the top bit, making this kind of mistake harmless, if misleading. Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: fsl: Reduce the size of interactive optionsSean Anderson2022-09-061-3/+3
| | | | | | | | | | | | | | | | The interactive mode uses large several tables of options which can be configured. However, much of the contents of these tables are repetetive. For example, no struct is larger than half a kilobyte, so the offset only takes up 9 bits. Similarly, the size is only ever 4 or 8, and printhex is a boolean. Reduce the size of these fields. This reduces the size of the options tables by around 10 KiB. However, the largest contributor to the size of the options tables is the use of a pointer for the strings. A better approach would be to use a separate array of strings, and store an integer index in the options tables. However, this would require a large re-architecting of this file. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to KconfigTom Rini2022-08-121-0/+7
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS And we remove the entries from the README for a number of already converted items. Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Drop display_options.h from common headerSimon Glass2022-08-101-0/+1
| | | | | | Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SYS_FSL_DDR_INTLV_256B to KconfigTom Rini2022-08-041-0/+7
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_INTLV_256B Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_DDR_RAW_TIMING to KconfigTom Rini2022-07-051-0/+7
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: Cleanup some emulator related options.Tom Rini2022-07-051-0/+6
| | | | | | | | - Drop the emulator CONFIG test from include/configs/ls1088ardb.h - Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in drivers/ddr/fsl/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SPL_COMMON_INIT_DDR to KconfigTom Rini2022-06-061-0/+14
| | | | | | | This converts the following to Kconfig: CONFIG_SPL_COMMON_INIT_DDR Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: fsl: Allow to compile it without env supportPali Rohár2022-04-261-0/+4
| | | | | | | | | When env support is disabled then usage of env_get_f() generates linker errors. So do not compile env_get_f() when env support is disabled (for example when disabled only in SPL). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* Convert CONFIG_DIMM_SLOTS_PER_CTLR to KconfigTom Rini2022-04-081-0/+4
| | | | | | | This converts the following to Kconfig: CONFIG_DIMM_SLOTS_PER_CTLR Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CHIP_SELECTS_PER_CTRL to KconfigTom Rini2022-03-031-0/+4
| | | | | | | | | | | | This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_BR0_PRELIM et al to KconfigTom Rini2021-12-011-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issueManinder Singh2021-11-091-2/+8
| | | | | | | | | Adds check for memory clock variable before calculating caslat_actual. Set mclk_ps to slowest DIMM supported if mclk_ps is found zero. Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* drivers: ddr: main.c: Fix Bad Shift operator issuePriyanka Singh2021-11-091-3/+8
| | | | | | | | Fix Bad Shift operator issue in step_to_string function by adding an if check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issuePriyanka Singh2021-11-091-3/+11
| | | | | | | | Fix possible divide by zero issue in fsl_ddr_set_memctl_regs by adding an if check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* drivers: ddr: util.c: Fix divide by zero issuePriyanka Singh2021-11-091-4/+8
| | | | | | | | Fix possible divide by zero issue in get_memory_clk_period_ps by adding a check Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* WS cleanup: remove SPACE(s) followed by TABWolfgang Denk2021-09-301-9/+9
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* nxp: Migrate a number of DDR related symbols to KconfigTom Rini2021-08-311-0/+21
| | | | | | | | | | - Guard most of the options in drivers/ddr/fsl/Kconfig with SYS_FSL_DDR || SYS_FSL_MMDC. - Migrate FSL_DMA, DDR_ECC, DDR_ECC_CMD, and ECC_INIT_VIA_DDRCONTROLLER to Kconfig. - Clean up the logic for including the DDR_ECC_CMD code. Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: Migrate DDR_SPD to KconfigTom Rini2021-08-311-0/+4
| | | | | | | | | Move the symbol that controls building some JEDEC SPD support functions to Kconfig. This is required on the TI keystone 2 platforms and very frequently (but not always) used on large number of Freescale/NXP platforms, so use imply there. Signed-off-by: Tom Rini <trini@konsulko.com>
* ppc: Remove T4160RDB boardTom Rini2021-07-071-2/+1
| | | | | | | | This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com>
* ppc: Remove sbc8641d boardTom Rini2021-07-073-95/+2
| | | | | | | | | | | This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. This is also the last of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well. Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ppc: Remove xpedite boardsTom Rini2021-07-071-1/+0
| | | | | | | | | | These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com>
* ppc: Remove MPC8555CDS boardsTom Rini2021-07-072-19/+4
| | | | | | | | | These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ppc: Remove MPC8541CDS boardTom Rini2021-07-072-2/+2
| | | | | | | | | This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ppc: Remove Cyrus_P5020 and P5040 boardsTom Rini2021-04-101-1/+0
| | | | | | | | | | | These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIOIgor Opaniuk2021-02-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_IS_ENABLED() macro, which provides more convenient way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs for both SPL and U-Boot proper. CONFIG_IS_ENABLED(DM_I2C) expands to: - 1 if CONFIG_SPL_BUILD is undefined and CONFIG_DM_I2C is set to 'y', - 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_DM_I2C is set to 'y', - 0 otherwise. All occurences were replaced automatically using these bash cmds: $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C/if !CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C/if CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C)/CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C_GPIO/if !CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C_GPIO/if CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C_GPIO)/CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: lx2162a: Add Soc changes to support LX2162AMeenakshi Aggarwal2020-12-101-0/+1
| | | | | | | | | | | | | | LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* common: rename getc() to getchar()Heinrich Schuchardt2020-10-221-1/+1
| | | | | | | | | | | | | | | | | | | The sandbox is built with the SDL2 library with invokes the X11 library which in turn calls getc(). But getc() in glibc is defined as int getc(FILE *) This does not match our definition. int getc(void) The sandbox crashes when called with parameter -l. Rename our library symbol getc() to getchar(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ddr: Rework errata A008109, A008378, 009942 workaroundJaiprakash Singh2020-06-043-65/+107
| | | | | | | | | Move errata A008109, A008378, 009942 workaround implementation from compute_fsl_memctl_config_regs() to fsl_ddr_set_memctl_regs() and add register write after each workaround implementation. Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* ddr: fsl: Impl. Erratum A008109Joakim Tjernlund2020-06-042-0/+9
| | | | | | | | Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-186-0/+6
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-188-0/+8
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bug.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-1815-0/+15
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-181-0/+1
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "mpc85xx: ddr: Always start DDR RAM in Self Refresh mode"Biwen Li2020-04-101-6/+7
| | | | | | | | | This reverts commit 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee. The commit breaks uboot boot (hang in ddr init) on many PowerPC boards like P3041DS, P4080DS Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* mpc85xx: ddr: Always start DDR RAM in Self Refresh modeJoakim Tjernlund2019-12-231-7/+6
| | | | | | | | | | | | Some of t1042 boards fails DDR init with an Automatic calibration error every now and then. Investigations revealed that true Warm boots never failed. Warm boots has some extra steps performed, one being to start DDRC in Self Refresh and then clearing SR right after. Applying this SR method unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* ddr, fsl: add DM_I2C supportHeiko Schocher2019-08-261-43/+76
| | | | | | | add DM_I2C support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* boards: lx2160a: Add support of I2C driver modelChuanhua Han2019-08-221-1/+35
| | | | | | | | | | | DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* env: Move env_get_f() to env.hSimon Glass2019-08-113-0/+3
| | | | | | | Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six2019-05-211-0/+4
| | | | | | | | CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* configs: fsl: move DDR specific defines to KconfigRajesh Bhagat2019-03-031-0/+12
| | | | | | | | | | | | | Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain2019-02-191-3/+6
| | | | | | | | | | | | fsl_ddr_board_options is generally defined in board board's ddr.c, but some boards like lx2160ardb board does not need this function. Defining fsl_ddr_board_options as weak function to resolve compilation errors for such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Fix checkpatch warnings] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain2018-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: fix '__hwconfig without a buffer' messagesJeremy Gebben2018-07-261-8/+6
| | | | | | | | | | Pass an empty buffer instead of NULL if the hwconfig environment variable isn't set. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Cc: Stefano Babic <sbabic@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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