u-boot.git - "Das U-Boot" Source Tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	x86: Re-enable PCAT timer 2 for beeping	Simon Glass	2013-05-13	1	-1/+5
\| \| \| \| \| \| \| \|	While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: Add TSC timer	Simon Glass	2013-05-13	1	-0/+103
	This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>