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* imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 onlyYe Li2023-03-293-3/+47
| | | | | | | | | | | | | This patch is used to support DBD owner fuse changed to S400 only. The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not configured by S400 default setting. So these PDAC and MSC are invalid, only DBD owner can access the corresponding resources. We have to configure necessary PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: upower: make code cleanerPeng Fan2023-03-291-12/+78
| | | | | | | | To clean the upower codes by aligning codes format, check err_code and add detail bits list for the memory magic number Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: upower: replace magic number with macroPeng Fan2023-03-291-1/+21
| | | | | | | | | | | | | The swton indicates the logic switch, magic number 0xfff80 is hard to understand, so use macro. Some board design may not have MIPI_CSI voltage input connected per data sheet. In that case, the upower power on API may dead loop mu to wait response, however there is no response. So remove MIPI_CSI here, let linux power domain driver to runtime enable the power domain. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Clear dividers in PLL3DIV_PFD registersYe Li2023-03-291-0/+3
| | | | | | | | | | | At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Reconfigure MRC3 for SRAM0 accessYe Li2023-03-291-0/+15
| | | | | | | | | Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode access only for boot purpose. Since SW will reuse the SRAM0 as SCMI buffer and SPL container loading buffer, need to reconfigure MRC3. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx8ulp: Change DRAM timing save area to 0x20055000Ye Li2023-03-291-1/+1
| | | | | | | | | To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
* imx: imx8ulp: configure XRDC for DRAM access from S400Ye Li2023-03-291-0/+5
| | | | | | | | Need to add DRAM access permission for S400, as S400 needs to access it When SPL calls image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li2023-03-294-23/+93
| | | | | | | | | | | | | | | | | | To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will hang. We use SIM GPR0 to pass the info from SPL to u-boot, because before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
* imx: imx8ulp: Remove the TRDC configure from A35Ye Li2023-03-291-18/+45
| | | | | | | | | | As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
* imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APDYe Li2023-03-291-0/+10
| | | | | | | | iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 partYe Li2023-03-291-1/+2
| | | | | | | | Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Get chip revision from SentinelYe Li2023-03-294-10/+34
| | | | | | | | | In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8ulp: Fix MU device probe failureYe Li2023-03-291-4/+2
| | | | | | | | Since latest DTS has added multiple MU nodes, using compatible string to find the device node is not proper. It finds the first node with the compatible string matched even the node is disabled. Signed-off-by: Ye Li <ye.li@nxp.com>
* Merge tag 'u-boot-at91-2023.07-a' of ↵Tom Rini2023-03-2812-42/+308
|\ | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.07 cycle: This feature set includes the clock changes required for sam9x60 SoC to support USB host.
| * configs: at91: sam9x60: Add required configs for the USB clockSergiu Moga2023-03-275-0/+5
| | | | | | | | | | | | | | | | | | | | Add the configs required to use the SAM9X60's USB clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> [claudiu.beznea: added CONFIG_AT91_SAM9X60_USB to sam9x60_curiosity_mmc1_defconfig] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: sam9x60: Add initial setup of UPLL and USBCK ratesSergiu Moga2023-03-271-0/+30
| | | | | | | | | | | | | | | | | | | | In order for some of the functionalities, such as the USB clocks, to work properly we need some clocks to be properly initialised at the very beginning of booting. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: pmc: export clock setup to pmcClaudiu Beznea2023-03-273-42/+64
| | | | | | | | | | | | | | | | | | Clock setup was intended for setting clocks at boot time on SAMA7G5, e.g. for root clocks like PLLs, that were used to feed IPs needed alive in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality to all at91 clocks as it may be necessary on other SoCs. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: sam9x60: Register the required clocks for USBSergiu Moga2023-03-271-0/+33
| | | | | | | | | | | | | | | | | | Register into DM the clocks required to properly enable USB functionality within the bootloader. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * clk: at91: Add support for sam9x60 USB clockSergiu Moga2023-03-274-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | Implement sam9x60 USB clock driver. This clock has three parents: PLLA, UPLL and MAINXTAL. The driver is aware of the three possible parents with the help of the two mux tables provied to the driver during the registration of the clock. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | Revert "rockchip: Fix early use of bootph props"Tom Rini2023-03-275-11/+11
| | | | | | | | | | | | | | | | | | While this change is correct for v2023.04 it is not correct for next (where this is right now) nor post-v2023.04. This reverts commit 8653e5d3b745925fced5fa6897c92f4a46ec2757. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' into nextTom Rini2023-03-27471-646/+1553
|\ \ | |/ |/|
| * Prepare v2023.04-rc5v2023.04-rc5Tom Rini2023-03-272-2/+2
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * configs: Resync with savedefconfigTom Rini2023-03-27334-352/+347
| | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge branch '2023-03-27-rockchip-rk3399-fixes'Tom Rini2023-03-275-55/+43
| |\ | | | | | | | | | | | | | | | - A series of minor cleanups to DISTRO_DEFAULTS and BOOTSTD so that the rk3399 bootstd migration can be complete and functional now, and make future migrations easier.
| | * rockchip: rk3399: Drop altbootcmdTom Rini2023-03-271-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The defined altbootcmd was specific to distro_bootcmd which is not longer in use on these platforms, so drop it. Tested-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
| | * rockchip: Use BOOTSTD_DEFAULTS if not DISTRO_DEFAULTSTom Rini2023-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd) we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd the general distro boot functionality will still work. Signed-off-by: Tom Rini <trini@konsulko.com>
| | * rockchip: Disable DISTRO_DEFAULTS for rk3399 boardsSimon Glass2023-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | These board have moved to standard boot but the old 'distro_bootcmd' command is still active. Disable DISTRO_DEFAULTS to fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| | * boot: Create a common BOOT_DEFAULTS for distro and bootstdSimon Glass2023-03-271-34/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These two features use a lot of common options. Move them into a common CONFIG to reduce duplication. Use 'select' for most options since these are things that boards aren't supposed to override. For now it is not possible to disable BOOT_DEFAULTS but we may take another look later. Note that five options use 'imply' to match existing behaviour. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Rework a bit so we don't grow so many platforms unintentionally] Signed-off-by: Tom Rini <trini@konsulko.com>
| | * lmb: Enable LMB if SYS_BOOT_RAMDISK_HIGHSimon Glass2023-03-271-0/+1
| | | | | | | | | | | | | | | | | | | | | Ramdisk relocation requires LMB, so enable it automatically to avoid build errors. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * Move DISTRO_DEFAULTS into boot/Simon Glass2023-03-272-27/+27
| | | | | | | | | | | | | | | | | | | | | This relates to booting so move it in to that Kconfig file, before changing it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: Drop bootstage stash in TPL and SPL for rockpro64Simon Glass2023-03-271-5/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately the IRAM used to stash the bootstage records in TPL becomes inaccessible after SPL runs. Presumably this is because of ATF taking it over. We could move the stash to another address in SPL, before passing it to U-Boot proper. But it seems easier to wait until we have support for standard passage[1] which should not be too far away. For now, disable it in TPL and SPL. [1] https://patchwork.ozlabs.org/project/uboot/cover/ 20220117150428.1580273-1-sjg@chromium.org/ Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2023-03-2715-7/+27
| |\ | | | | | | | | | - x86: Bug fixes of previous BayTrail platform CONFIG_TEXT_BASE changes
| | * x86: som-db5800-som-6867: Fix up adjustment of CONFIG_TEXT_BASESimon Glass2023-03-272-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: e23cae30801f ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: dfi-bt700: Fix up adjustment of CONFIG_TEXT_BASESimon Glass2023-03-273-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: 5d1c8342aeaa ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: conga-qeval20-qa3-e3845: Fix up adjustment of CONFIG_TEXT_BASESimon Glass2023-03-275-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: 388f93f96354 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * x86: bayleybay: Fix up adjustment of CONFIG_TEXT_BASESimon Glass2023-03-272-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Fixes: f38be3086837 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: minnowmax: Fix up adjustment of CONFIG_TEXT_BASESimon Glass2023-03-273-3/+15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | With recent CONFIG_TEXT_BASE changes, there are inconsistencies between several settings. Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC cache out of the way too. Add documentation on how to make this change safely. Fixes: 66e2c665f3b6 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * Merge tag 'efi-2023.04-rc5' of ↵Tom Rini2023-03-253-12/+46
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023.04-rc5 UEFI: * Create unique device paths for USB devices with the same vendor and product id.
| | * efi_loader: fix device-path for USB devicesHeinrich Schuchardt2023-03-251-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFI device paths for block devices must be unique. If a non-unique device path is discovered, probing of the block device fails. Currently we use UsbClass() device path nodes. As multiple devices may have the same vendor and product id these are non-unique. Instead we should use Usb() device path nodes. They include the USB port on the parent hub. Hence they are unique. A USB storage device may contain multiple logical units. These can be modeled as Ctrl() nodes. Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| | * efi_loader: support for Ctrl() device path nodeHeinrich Schuchardt2023-03-252-0/+13
| |/ | | | | | | | | | | | | | | | | * Add the definitions for Ctrl() device path nodes. * Implement Ctrl() nodes in the device path to text protocol. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * Merge branch 'rpi-2023.04' of ↵Tom Rini2023-03-245-23/+158
| |\ | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - Fixes for booting newer revs of the SoC in the Raspberry Pi 4 - Propagate some firmware DT properties to the loaded DT - Update the Zero2W upstream DT name
| | * mmc: bcm2835-host: let firmware manage the clock divisorVincent Fazio2023-03-244-21/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer firmware can manage the SDCDIV clock divisor register, allowing the divisor to scale with the core as necessary. Leverage this ability if the firmware supports it. Adapted from the following raspberrypi Linux kernel commit: bcm2835-sdhost: Firmware manages the clock divisor https://github.com/raspberrypi/linux/commit/08532d242d7702ae0add95096aa49c5e96e066e2 Signed-off-by: Vincent Fazio <vfazio@xes-inc.com> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| | * arm: rpi: fallback to max clock rate for MMC clockVincent Fazio2023-03-242-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1, the GET_CLOCK_RATE mailbox property was changed to return the last value set by SET_CLOCK_RATE. https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502 Due to this change in firmware behavior, bcm2835_get_mmc_clock now returns a clock rate of zero since we do not issue SET_CLOCK_RATE. This results in degraded MMC performance. SET_CLOCK_RATE fixes the clock to a specific value and disables scaling so is not an ideal solution. Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if GET_CLOCK_RATE returns zero. Signed-off-by: Vincent Fazio <vfazio@xes-inc.com> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| | * rpi: Update the RPi Zero 2W DT filenamePeter Robinson2023-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | Update the Raspberry Pi Zero 2W device tree file name to match what landed upstream. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| | * rpi: Copy eth PHY address from fw DT to loaded DTAntoine Mazeas2023-03-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Raspberry Pi 400 boards, specifically rev 1.1, have a different address for the ethernet PHY device than what is provided by the kernel DTB. The correct address is provided by the firmware, so we should carry it over into the loaded device tree so that ethernet works on such boards. Signed-off-by: Antoine Mazeas <antoine@karthanis.net> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| | * rpi: Copy properties from firmware dtb to the loaded dtbAntoine Mazeas2023-03-141-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RPI firmware adjusts several property values in the dtb it passes to u-boot depending on the board/SoC revision. Inherit some of these when u-boot loads a dtb itself. Specificaly copy: * /model: The firmware provides a more specific string * /memreserve: The firmware defines a reserved range, better keep it * emmc2bus and pcie0 dma-ranges: The C0T revision of the bcm2711 Soc (as present on rpi 400 and some rpi 4B boards) has different values for these then the B0T revision. So these need to be adjusted to boot on these boards * blconfig: The firmware defines the memory area where the blconfig stored. Copy those over so it can be enabled. * /chosen/kaslr-seed: The firmware generates a kaslr seed, take advantage of that. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Signed-off-by: Antoine Mazeas <antoine@karthanis.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
| * | Merge branch '2023-03-22-assorted-fixes'Tom Rini2023-03-2210-15/+28
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Assorted TI platform fixes, correct location of NXP boot format git repository, don't try and mount partitions that are too small to be ext4 as ext4, handle .bin files in .gitattributes, flush out panic messages for sure, and correct console location on Arm total_compute.
| | * | dma: ti: k3-udma: Fix channel hang on teardownVignesh Raghavendra2023-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting RX flow error handling will stall the channel until descriptors are available to move RX data. Setting this bit causes issues when tearing down ethernet DMA channel at the end of TFTP transfer as unrelated network packets can cause teardown to stall indefinitely waiting for driver to queue add more desc leading to channel hang with error logs: udma_stop_dev2mem TIMEOUT ! udma_stop_dev2mem: peer not stopped TIMEOUT ! udma_stop_dev2mem TIMEOUT ! Fix this by clearing rx_error_handling similar to how its done for UDMA as part of udma_alloc_rchan_sci_req() This fixes occasional TFTP Failures seen when downloading multiple files one after the other on AM64/AM62 SoCs. Fixes: 9a92851c33e8 ("dma: ti: k3-udma: Add BCDMA and PKTDMA support") Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| | * | fs: ext4: check the minimal partition size to mountPatrick Delaunay2023-03-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to mount a too small partition to handle a EXT4 file system. This patch add a test on partition size before to read the SUPERBLOCK_SIZE buffer and avoid error latter in fs_devread() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * | gitattributes: Treat .bin files as binary.Sebastian Andrzej Siewior2023-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Binary files, which are committed to a private fork of this repository, will be subject to line feed substitution unless marked as binary. Mark .bin files as binary. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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