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* x86: Move UCLASS_IRQ into a separate fileSimon Glass2019-12-156-5/+152
| | | | | | | | | | | Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations. Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Add PCI driver and test for p2sbSimon Glass2019-12-1513-0/+428
| | | | | | | | Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: Disable mmio by default in testsSimon Glass2019-12-151-0/+1
| | | | | | | | When reseting sandbox for tests, disable mmio support since that is the default state. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add support for p2sb uclassSimon Glass2019-12-155-0/+386
| | | | | | | | | | | | | The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. This adds a uclass and enables it for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: sandbox: Add a PMC emulator and testSimon Glass2019-12-1514-0/+510
| | | | | | | Add a simple PMC for sandbox to permit tests to run. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: power: Add an ACPI PMC uclassSimon Glass2019-12-156-0/+406
| | | | | | | | | Intel x86 SoCs have a power manager/controller which handles several power-related aspects of the platform. Add a uclass for this, with a few useful operations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unnecessary interrupt code for TPLSimon Glass2019-12-151-0/+2
| | | | | | | | We don't expect an exception in TPL and don't need to set up interrupts in TPL. Drop this whole file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unnecessary cpu code for TPLSimon Glass2019-12-152-4/+41
| | | | | | | | | | We don't need to know every detail about the CPU in TPL. Drop some superfluous functions to reduce code size. Add a simple CPU detection algorithm which just supports Intel and AMD, since we only support TPL on Intel, so far. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: Reduce timer code size in TPL on Intel CPUsSimon Glass2019-12-152-2/+14
| | | | | | | | | | | | | | | Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: use a timer base of 0Simon Glass2019-12-155-1/+19
| | | | | | | | | | | | | | | | On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* board_r: Move early-timer init laterSimon Glass2019-12-151-5/+14
| | | | | | | | | | | | | | | At present the early timer init happens as soon as driver model is set up. This makes it impossible to do anything that needs driver model but must run before devices are probed (as needed with Intel's FSP-S, for example). In any case it is not a good idea to tie probing of particular drivers too closely to the DM init. Create a new function to init the timer and put it a bit later in the sequence. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pinctrl: Allow enabling full pinctrl in SPL/TPLSimon Glass2019-12-151-0/+14
| | | | | | | | At present these options cannot be enabled for SPL/TPL, but this can be useful in some cases. Add Kconfig options to allow it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* fdt: Show the preprocessed .dts file on errorSimon Glass2019-12-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When device-tree compilation fails it is sometimes tricky to see which line is broken, since the input file to dtc is a pre-processed version of the device tree. Add a line that points to the file that needs to be checked: When the error is in the main .dts file, output is something like this: output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47 syntax error FATAL ERROR: Unable to parse input tree but in fact looking at that file shows nothing useful: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) Instead we need to look at the preprocessed file, which shows: 163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1) Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is not being resolved by the preprocessor. This commit adds an additional useful message: Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors Note that if the error is reported in an included file, such as u-boot.dtsi then the output is the following: Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error FATAL ERROR: Unable to parse input tree But again, if the error is due to a preprocessor failure, like this: filename = CONFIG_IFW_INPUT_FILE; then you can't tell what the problem is by looking at the source. All you see is the original code: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; }; intel-fsp-m { filename = CONFIG_FSP_FILE_M; }; Everything looks fine. But looking at the output of the preprocessor: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; intel-fsp-m { filename = "fsp_m.bin"; }; This shows that the filename (normally "fitimage.bin") has not been inserted the preprocess, leading to the realisation that the value should be CONFIG_IFWI_INPUT_FILE. If the above does not make sense, I encourage people to try introducing errors in the device tree preprocessed values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spi: Add helper functions for Intel Fast SPISimon Glass2019-12-154-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Support use in SPLSimon Glass2019-12-151-3/+40
| | | | | | | | | | | | Allow this driver to set up an IO address in SPL using an 'early-regs' property. This allows SPL to use the I2C driver without having to enable the full PCI stack. Also split out ofdata_to_platdata in designware driver since this is more correct, and more convenient for the new logic. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Avoid using static dataSimon Glass2019-12-152-3/+7
| | | | | | | | | | | Drivers are not allowed to use static data since they may be used in SPL where BSS is not available. It is possible that driver model may provide support for numbering devices in the future. But for now, move this to global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i2c: designware: Tidy up PCI supportSimon Glass2019-12-154-89/+134
| | | | | | | | | | | | | | | | This is hacked into the driver at present. It seems better to have it as a separate driver that uses the base driver. Create a new file and put the X86 code into it. Actually the Baytrail settings should really come from the device tree. Note that 'has_max_speed' is added as well. This is currently always false but since only Baytrail provides the config, it does not affect operation for other devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* net: Move the checksum functions to lib/Simon Glass2019-12-154-61/+49
| | | | | | | | | | | | | | | These functions are used by code outside the network support, so move them to lib/ to be more accessible. Without this, the functions are only accessible in SPL/TPL only if CONFIG_SPL/TPL_NET are defined. Many boards do not enable those option but still want to do checksums in this format. Fix up a few code-style nits while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_get_devfn() into a common fileSimon Glass2019-12-154-26/+65
| | | | | | | | | | | | | | | Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined. To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined. Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Allow delaying auto-config until after relocationSimon Glass2019-12-153-6/+42
| | | | | | | | | | | | | | At present PCI auto-configuration happens in U-Boot both before and after relocation. This is a waste of time and may mess up static addresses used in board_init_f(). Adjust the code to supporting doing auto-configuration once, after relocation, under control of a device-tree property. This is needed for Apollo Lake for debugging the silicon-init code. Once the UART is moved to a different MMIO address the debug UART does not work and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Fix offset_to_ofnode() with invalid offsetSimon Glass2019-12-151-1/+1
| | | | | | | | | | | | | | | | If the offset is -1 this function correctly sets up a null ofnode. But if the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it does the wrong thing. An offset of -1 in ofnode indicates that the ofnode is not valid. Any other negative value is not handled by ofnode_valid(). We could of course change that function, but it seems much better to always use the same value for an invalid node. Fix it by setting the offset to -1 if it is invalid for any reason. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: gpio: Allow control of GPIO uclass in SPLSimon Glass2019-12-1542-82/+112
| | | | | | | | | | | | | | | | | | | | At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* binman: Add a library to access binman entriesSimon Glass2019-12-155-0/+114
| | | | | | | | | | | SPL and TPL can access information about binman entries using link-time symbols but this is not available in U-Boot proper. Of course it could be made available, but the intention is to just read the device tree. Add support for this, so that U-Boot can locate entries. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'dm-next-13dec19' of ↵Tom Rini2019-12-1212-50/+158
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * cros_ec: use uint instead of uint8_t for cmd paramMichael Auchter2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Chromium EC commands can be up to 16-bits, so using a uint8_t here can cause truncation. Update to use a uint instead. It looks like this should likely have been done as a part of 9fea76f5d30264dc08ac591a7a89427b8441555b, but this function was skipped for some reason. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * buildman: Ignore blank lines during size checksTom Rini2019-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | Today when parsing the .sizes files we get a warning about an invalid line in the file as it's blank. Solve this by checking that we have a non-blank line prior to processing. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * buildman: Add options to get the arch and toolchain infoSimon Glass2019-12-105-0/+86
| | | | | | | | | | | | | | | | | | Sometimes it is useful for external tools to use buildman to provide the toolchain information. Add an -a option which shows the value to use for the ARCH environment variable, and -A which does the same for CROSS_COMPILE Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Figure out boards before commitsSimon Glass2019-12-101-30/+29
| | | | | | | | | | | | | | | | | | At present buildman looks at toolchains, then commits and then boards. Move the board processing up above the commit processing, since it relates to the toolchain code. This will make it easier to check the toolchains needed for a board without processing commits first. Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Ask genboardscfg to be quietSimon Glass2019-12-101-1/+1
| | | | | | | | | | | | Now that this tool has a 'quiet' flag, use it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * genboardcfg: Support a quiet modeSimon Glass2019-12-101-3/+7
| | | | | | | | | | | | | | We don't really need buildman to print this every time it runs. Add a flag to run quietly, that buildman can use. Signed-off-by: Simon Glass <sjg@chromium.org>
| * test.py: Make search for autoconf.mk more permissiveSimon Glass2019-12-101-12/+27
| | | | | | | | | | | | | | | | Buildman doesn't store this file in the same directory as a normal build. Update the conftest code to handle both cases. Change-Id: I1fd0e56054d7dc77394a7589336aa0991bd0133d Signed-off-by: Simon Glass <sjg@chromium.org>
| * buildman: Improve [make-flags] section parser to allow quoted stringsCristian Ciocaltea2019-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser responsible for the '[make-flags]' section in the '.buildman' settings file is currently not able to handle quoted strings, as given in the sample bellow: [make-flags] qemu_arm=HOSTCC="cc -isystem /add/include" HOSTLDFLAGS="-L/add/lib" This patch replaces the simple string splitter based on the <space> delimiter with a regex tokenizer that preserves spaces inside double quoted strings. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
| * serial: sandbox: support UnicodeHeinrich Schuchardt2019-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | Due to a conversion error the sandbox does not accept byte values 0x80-0xff from the keyboard. The UEFI extended text input unit test requires Unicode support. Use unsigned char for the serial buffer. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
| * sandbox: add missing compatible property in device treeHeinrich Schuchardt2019-12-102-0/+2
| | | | | | | | | | | | | | | | | | In the device tree UEFI unit test the compatible property of the device is read. Provide the missing property. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'rpi-next-2020.01.2' of ↵Tom Rini2019-12-112-5/+8
|\ \ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - fix DRAM bank detection for unified binary - fix 32bit RPi4 config
| * | ARM: defconfig: Fix 32bit config for RPi4Matthias Brugger2019-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rpi_4_32b_defconfig states that only one DRAM bank is present. This leads to a wrong configuration of the available DRAM. Fix this by setting the DRAM bank config accordingly. Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | rpi: Enable DRAM bank initialization on arm64Matthias Brugger2019-12-111-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now we only update the DRAM banks when we are define CONFIG_BCM2711. But our one binary approach uses a config that supports BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on Raspberry Pi 4, even if it has more RAM. Fix this by calling dram_init_banksize. Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | rpi: fix dram bank initializationMatthias Brugger2019-12-111-2/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To update the dram bank information from device-tree we use fdtdec_decode_ram_size() which expectes the the size-cells and address-cells to be defined in the memory node. For normal system RAM these values are defined in the root node. When the values differ from the default values defined in the spec, we can end up with wrong RAM bank information. Switch to the "standard" way to update the RAM bank information to avoid this. Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* | Merge tag 'fix-for-2020.01' of ↵Tom Rini2019-12-111-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2020.01 - i2c: i2c_cdns: fix write timeout on fifo boundary fixes timout issue when writting number of bytes is multiple of the FIFO depth.
| * | i2c: i2c_cdns: fix write timeout on fifo boundaryMichael Auchter2019-12-111-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'u-boot-atmel-fixes-2020.01-a' of ↵Tom Rini2019-12-117-10/+34
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel - First set of u-boot-atmel fixes for 2020.01 cycle: This set includes a small fix for gpio bank names, one for removing unused headers (also touches some other boards), and a fix for the QSPI env read on one of the boards.
| * | configs: sama5d27_som1_ek: Add default config to read ENV from QSPISwapna Gurumani2019-12-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | In the initial SPI flash setup, the default bus mode being used was 3, which is incorrect, causing a CRC error when the ENV was being read from QSPI. Setting the default bus mode to 0 which is the correct mode. Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
| * | gpio: at91_gpio: Add bank namesJames Byrne2019-12-031-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | Make the at91_gpio driver set sensible GPIO bank names in the platform data. This makes the 'gpio status' command a lot more useful. Signed-off-by: James Byrne <james.byrne@origamienergy.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | board: Remove unnecessary inclusion of micrel.h from boardsJames Byrne2019-12-035-7/+0
| | | | | | | | | | | | | | | | | | | | | Several boards still unnecessarily included micrel.h but no longer require it since the switch to Device Tree configuration. Signed-off-by: James Byrne <james.byrne@origamienergy.com>
* | | Merge tag 'fixes-for-2020.01' of ↵Tom Rini2019-12-10108-16/+195
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix crash and board reset when drawing RLE8 bitmaps bigger than the framebuffer resolution - reduce dead code in video and console uclass routines (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1, stm32f746-disco, stm32f769-disco and wandboard)
| * | video: make BPP and ANSI configs optionalAnatolij Gustschin2019-12-06105-9/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards do not use all selected framebuffer depth configurations, for such boards there is some unused code in video and console uclass routines. Make depth specific code optional to avoid dead code and slightly reduce binary size. Also make ANSI code optional for the same reason. When i.e. using only VIDEO_BPP16 the code size shrinks (below values when using gcc-7.3.0): $ ./tools/buildman/buildman -b video-wip -sS wandboard ... 01: Merge git://git.denx.de/u-boot-sh 02: video: add guards around 16bpp/32bbp code 03: video: make BPP and ANSI configs optional arm: (for 1/1 boards) all -776.0 bss -8.0 text -768.0 Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
| * | video: add guards around 16bpp/32bbp codeAnatolij Gustschin2019-12-062-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards use only single depth configuration, for such boards there is some unused code in video and console uclass routines. Add guards to avoid dead code. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Patrice Chotard <patrice.chotard@st.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
| * | video: bmp: Fix video_display_rle8_bitmap()Patrice Chotard2019-12-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the BMP size is bigger than the frame buffer, don't use the BMP's width and height in video_display_rle8_bitmap, but the one's checked in video_bmp_display() as parameters to video_display_rle8_bitmap(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> CC: Yannick Fertré <yannick.fertre@st.com>
| * | video: bmp: Fix video_splash_align_axis()Patrice Chotard2019-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert panel_picture_delta and axis_alignment from unsigned long to long to insure to store correctly the difference between panel_size and picture_size in case the panel_size is smaller than picture_size. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> CC: Yannick Fertré <yannick.fertre@st.com> [agust: change axis_alignment to long] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2019-12-0933-73/+1057
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
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