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* mmc: exynos_dw_mmc: remove unused functionJaehoon Chung2021-01-131-56/+0
| | | | | | | | Remove unused function in exynos_dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: arndale: remove board_mmc_init functionJaehoon Chung2021-01-132-15/+0
| | | | | | | | | | Remove board_mmc_init function. It will be probed with driver-model. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge tag 'ti-v2021.04-rc1' of ↵Tom Rini2021-01-12109-1226/+6045
|\ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - DM support for OMAP PWM backlight - USB host mode support for AM654 - Minor SPI fixes - Add support k2g ice board with 1GHz silicon - Fix GTC programming for K3 devices
| * remoteproc: ti_k3_arm64: Program CNTFID0 register in GTCNishanth Menon2021-01-121-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8's generic timer[1] picks up it's graycode from GTC. However, the frequency of the GTC is supposed to be programmed in CNTFID0[2] register prior to enabling the GTC in CNTCR[3] register. In K3 architecture, GTC provides a central time to many parts of the SoC including graycode to the generic timer in the ARMv8 subsystem. However, due to the central nature and the need to enable the counter early in the boot process, the R5 based u-boot enables GTC and programs it's frequency based on central needs of the system. This may not be a constant 200MHz based on the system. The bootloader is supposed to program the FID0 register with the correct frequency it has sourced for GTC from the central system controller OR from PLLs as appropriate, and TF-A is supposed[4] to use that as the frequency for it's local timer. Currently we are programming just the CNTCR[3] register to enable the GTC, however we dont let TF-A know the frequency that GTC is actually running at. A mismatch in programmed frequency and what we program for generic timer will, as we can imagine, all kind of weird mayhem. So, program the CNTFID0 register with the clock frequency. Note: assigned-clock-rates should have set the clock frequency, so the only operation we need to explicitly do is to retrieve the frequency and program it in FID0 register. Since the valid in K3 for GTC clock frequencies are < U32_MAX, we can just cast the ulong and continue. [1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary [2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0 [3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr [4] https://github.com/ARM-software/arm-trusted-firmware/commit/6a22d9ea3c7fa28d053d3ba264b49b7396a86f9e Signed-off-by: Nishanth Menon <nm@ti.com>
| * arm: dts: k3-*-r5-*-board: Add GTC clockNishanth Menon2021-01-123-0/+3
| | | | | | | | | | | | | | Add GTC Clock definition as index 0 clock so that we can use the clock node in the driver later on. Signed-off-by: Nishanth Menon <nm@ti.com>
| * Nokia RX-51: Add test for U-Boot serial consolePali Rohár2021-01-121-1/+32
| | | | | | | | | | | | | | | | | | This patch adds a new test which checks that U-Boot for Nokia RX-51 running in qemu can print test line to serial console and also checks that test line appeared on qemu serial console. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Pavel Machek <pavel@ucw.cz>
| * Nokia RX-51: Do not try calling both ext2load and ext4loadPali Rohár2021-01-121-14/+3
| | | | | | | | | | | | | | | | Those two commands now doing same thing, reading from ext2/3/4 filesystem. So remove useless duplicated call. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz>
| * board: ti: am335x-ice: get CDCE913 clock deviceDario Binacchi2021-01-122-2/+2
| | | | | | | | | | | | | | With support for other clock drivers, the potentially supported CDCE913 device can no longer be probed without specifying its DT node name. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: omap: move drivers to 'ti' directoryDario Binacchi2021-01-1212-9/+22
| | | | | | | | | | | | | | Add drivers/video/ti/ folder and move all TI's code in this folder for better maintenance. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: omap: split the legacy code from the DM codeDario Binacchi2021-01-127-374/+468
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The schedule for deprecating the features of the pre-driver-model puts 2019.17 as the deadline for the video subsystem. Furthermore, the latest patches applied to the am335x-fb.c module have decreased the amount of code shared with the pre-driver-model implementation. Splitting the two implementations into two modules improves the readability of the code and will make it easier to drop the pre-driver-model code. I have not created a header file with the data structures and the constants for accessing the LCD controller registers, but I preferred to keep them inside the two c modules. This is a code replication until the pre-driver-model version is dropped. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: omap: set LCD clock rate through DM APIDario Binacchi2021-01-121-26/+103
| | | | | | | | | | | | | | | | | | | | | | The patch configures the display DPLL using the functions provided by the driver model API for the clock. The device tree contains everything needed to get the DPLL clock. The round rate function developed for calculating the DPLL multiplier and divisor and the platform routines for accessing the DPLL registers are removed from the LCD driver code because they are implemented inside the DPLL clock driver. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: omap: drop domain clock enabling by SOC apiDario Binacchi2021-01-121-1/+1
| | | | | | | | | | | | | | Enabling the domain clock is performed by the sysc interconnect target module driver during the video device probing. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * video: omap: add panel driverDario Binacchi2021-01-1216-194/+464
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous version of am335x-fb.c contained the functionalities of two drivers that this patch has split. It was a video type driver that used the same registration compatible string that now registers a panel type driver. The proof of this is that two compatible strings were referred to within the same driver. There are now two drivers, each with its own compatible string, functions and API. Furthermore, the panel driver, in addition to decoding the display timings, is now also able to manage the backlight. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: core: add a function to decode display timingsDario Binacchi2021-01-124-0/+156
| | | | | | | | | | | | | | | | The patch adds a function to get display timings from the device tree node attached to the device. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * bus: ti: am33xx: add pwm subsystem driverDario Binacchi2021-01-123-0/+28
| | | | | | | | | | | | | | | | | | | | | | The TI PWMSS driver is a simple bus driver for providing clock and power management for the PWM peripherals on TI AM33xx SoCs, namely eCAP, eHRPWM and eQEP. For DT binding details see Linux doc: - Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * pwm: ti: am33xx: add enhanced pwm driverDario Binacchi2021-01-123-0/+476
| | | | | | | | | | | | | | | | | | | | | | | | | | Enhanced high resolution PWM module (EHRPWM) hardware can be used to generate PWM output over 2 channels. This commit adds PWM driver support for EHRPWM device present on AM33XX SOC. The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * arm: dts: am335x: enable scm_clocks auto bindingDario Binacchi2021-01-122-0/+16
| | | | | | | | | | | | | | Adding the 'simple-bus' compatible string to the scm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * omap: timer: fix the rate settingDario Binacchi2021-01-121-3/+3
| | | | | | | | | | | | | | The prescaler (PTV) setting must be taken into account even when the timer input clock frequency has been set. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * fdt: translate address if #size-cells = <0>Dario Binacchi2021-01-129-15/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __of_translate_address routine translates an address from the device tree into a CPU physical address. A note in the description of the routine explains that the crossing of any level with since inherited from IBM. This does not happen for Texas Instruments, or at least for the beaglebone device tree. Without this patch, in fact, the translation into physical addresses of the registers contained in the am33xx-clocks.dtsi nodes would not be possible. They all have a parent with #size-cells = <0>. The CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS symbol makes translation possible even in the case of crossing levels with #size-cells = <0>. The patch acts conservatively on address translation, except for removing a check within the of_translate_one function in the drivers/core/of_addr.c file: + ranges = of_get_property(parent, rprop, &rlen); - if (ranges == NULL && !of_empty_ranges_quirk(parent)) { - debug("no ranges; cannot translate\n"); - return 1; - } if (ranges == NULL || rlen == 0) { offset = of_read_number(addr, na); memset(addr, 0, pna * 4); debug("empty ranges; 1:1 translation\n"); There are two reasons: 1 The function of_empty_ranges_quirk always returns false, invalidating the following if statement in case of null ranges. Therefore one of the two checks is useless. 2 The implementation of the of_translate_one function found in the common/fdt_support.c file has removed this check while keeping the one about the 1:1 translation. The patch adds a test and modifies a check for the correctness of an address in the case of enabling translation also for zero size cells. The added test checks translations of addresses generated by nodes of a device tree similar to those you can find in the files am33xx.dtsi and am33xx-clocks.dtsi for which the patch was created. The patch was also tested on a beaglebone black board. The addresses generated for the registers of the loaded drivers are those specified by the AM335x reference manual. Signed-off-by: Dario Binacchi <dariobin@libero.it> Tested-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * clk: move clk-ti-sci driver to 'ti' directoryDario Binacchi2021-01-125-9/+9
| | | | | | | | | | | | | | The patch moves the clk-ti-sci.c file to the 'ti' directory along with all the other TI's drivers, and renames it clk-sci.c. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * arm: dts: am335x: enable prcm_clocks auto bindingDario Binacchi2021-01-121-0/+4
| | | | | | | | | | | | | | Adding the 'simple-bus' compatible string to the prcm_clocks node will allow its automatic binding. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: omap4: add clock manager driverDario Binacchi2021-01-122-1/+23
| | | | | | | | | | | | | | | | | | This minimal driver is only used to bind child devices. For DT binding details see Linux doc: - Documentation/devicetree/bindings/arm/omap/prcm.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add support for clkctrl clocksDario Binacchi2021-01-123-0/+161
| | | | | | | | | | | | | | | | | | | | | | Until now the clkctrl clocks have been enabled/disabled through platform routines. Thanks to this patch they can be enabled and configured directly by the probed devices that need to use them. For DT binding details see Linux doc: - Documentation/devicetree/bindings/clock/ti-clkctrl.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * ti: am33xx: fix do_enable_clocks() to accept NULL parametersDario Binacchi2021-01-121-4/+6
| | | | | | | | | | | | | | | | | | Up till this commit passing NULL as input parameter was allowed, but not handled properly. When a NULL parameter was passed to the function a data abort was raised. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: dts: am335x: include am33xx-u-boot.dtsiDario Binacchi2021-01-1211-0/+23
| | | | | | | | | | | | Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add gate clock driverDario Binacchi2021-01-123-0/+100
| | | | | | | | | | | | | | | | | | The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add divider clock driverDario Binacchi2021-01-126-25/+439
| | | | | | | | | | | | | | | | | | | | | | | | The patch adds support for TI divider clock binding. The driver uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/divider.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/divider.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: am33xx: add DPLL clock driversDario Binacchi2021-01-124-0/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macroDario Binacchi2021-01-121-0/+1
| | | | | | | | | | | | | | Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in idle bypass fast relock mode. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add mux clock driverDario Binacchi2021-01-125-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: add clk_round_rate()Dario Binacchi2021-01-127-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
| * arm: dts: sync am33xx with Linux 5.9-rc7Dario Binacchi2021-01-1210-542/+2273
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been several changes to the am33xx.dtsi, so this patch re-syncs it with Linux. Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel. With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. The am33xx-clock.dtsi file is the same as that of the Linux kernel, except for the reg property of the node l4-wkup-clkctrl@0. As for the am33xx.dtsi file, all the devices with drivers not yet implemented and those I was able to test with this patch have been moved to am33xx-l4.dtsi. In case of any regressions, problem devices can be reverted by moving them back and removing the related interconnect target module node. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * bus: ti: add minimal sysc interconnect target driverDario Binacchi2021-01-125-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7Dario Binacchi2021-01-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PRUSS SYSC type: The PRUSS module has a SYSCFG which is unique. The SYSCFG has two additional unique fields called STANDBY_INIT and SUB_MWAIT in addition to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this new sysc type. Add support for MCAN on dra76x: The dra76x MCAN generic interconnect module has a its own format for the bits in the control registers. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: export generic routinesDario Binacchi2021-01-122-12/+69
| | | | | | | | | | | | | | | | Export routines that can be used by other drivers avoiding duplicating code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm:pdu001: Use pseudo partition UUID for LINUX kernel boot paramter rootFelix Brack2021-01-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As more and more LINUX drivers are modified to use asynchronous probing instead of synchronous probing, relying on device names being equal in U-Boot and LINUX is not possible anymore. This is also true for block device names like mmc0, mmc1 ect. With LINUX kernel commit a1a4891 the probing type for the sdhci-omap driver has been set to asynchronous mode too (probe_type is now PROBE_PREFER_ASYNCHRONOUS). In the case of the PDU001 board this results in the devices mmc0 and mmc1 being swapped between U-Boot and LINUX. Device mmc0 in U-Boot becomes mmc1 in LINUX an vice versa. Hence using device name identifiers with LINUX kernel parameter root does not work anymore. This patch changes the LINUX kernel boot parameter root to use the pseudo (since we use MBR not GPT) partition UUID to locate the partition hosting the root file system. Signed-off-by: Felix Brack <fb@ltec.ch>
| * board: ti: k2g: Add support for K2G ICE with 1GHz SiliconLokesh Vutla2021-01-126-6/+19
| | | | | | | | | | | | Add board detection support for K2G ICE with FlagChip 1GHz silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-j721e: ddr: Update to 0.5.0 version of DDR config toolPraneeth Bajjuri2021-01-122-219/+219
| | | | | | | | | | | | | | | | Update the ddr settings to use the DDR reg config tool rev 0.5.0. This enables 4266MTs DDR configuration. Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com>
| * spi: omap3_spi: Fix speed and mode selectionVignesh Raghavendra2021-01-121-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdataOvidiu Panait2021-01-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
| * gpio: tca642x: fix input subcommand for gpio banks > 0Tomas Novotny2021-01-121-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The value of input pin for bank > 0 is always 0 for input subcommand. The reason is that gpio_bank variable is computed only for invert and output subcommands (it depends on number of arguments). The default value of zero causes to shift the mask away for banks > 0. Please note that info subcommand works as expected, because the input pin values are accessed differently. Fixes: 61c1775f16ed ("gpio: tca642x: Add the tca642x gpio expander driver") Cc: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tomas Novotny <tomas@novotny.cz>
| * configs: am65x_evm: Define the maximum file size for DFUAswath Govindraju2021-01-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In include/dfu.h, if CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then it is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE. This is 128 KiB for a53 core and 20 KiB for r5 core. If a larger file is transferred using dfu then it fails. CONFIG_SYS_DFU_DATA_BUF_SIZE can not be increased as there is not enough heap memory to be allocated for the buffer in case of R5 spl. Fix this by defining CONFIG_SYS_DFU_MAX_FILE_SIZE as the default CONFIG_SYS_DFU_DATA_BUF_SIZE value. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * arm: dts: am654-base-board-uboot: Add aliases for USB subsystemsAswath Govindraju2021-01-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence number assigned for USB subsystem in a uclass is dependent on the order of occurrence in the device tree. If the dr_mode of USB3SS0 controller is varied then the sequence number of USB3SS1 controller also changes. If aliases are added then sequence numbers are assigned using the alias number. This makes the sequence number of USB3SS1 controller independent of USB3SS0 controller's dr_mode. Therefore, add aliases to fix the sequence number assigned to the USB subsystems. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * arm: dts: am654-base-board-uboot: Set USB0 dr_mode to hostAswath Govindraju2021-01-121-1/+1
| | | | | | | | | | | | | | USB3SS0 controller is to be used as a host in U-boot. Fix it by changing the dr_mode to host. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * board: ti: am65x: Set SERDES0 mux to PCIe to use USB 2.0 interfaceAswath Govindraju2021-01-121-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this issue is not present. Implement this workaround by writing 1 to LANE_FUNC_SEL field in CTRLMMR_SERDES0_CTRL register. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
* | Merge tag 'u-boot-atmel-2021.04-a' of ↵Tom Rini2021-01-1262-50/+739
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2021.04 cycle This feature set includes the new board SAMA7G5 EK, the new evaluation kit for Microchip AT91 SAMA7G5 SoC . The current board support includes two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and support for two Ethernet interfaces.
| * | ARM: dts: sama7g5ek: fix TXC pin configurationNicolas Ferre2021-01-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TXC line is directly connected from the SoC to the KSZ9131 PHY. There is a transient state on this signal, before configuring it to RGMII, which leads to packet transmit being blocked. Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
| * | configs: sama7g5ek: add i2c and eepromEugen Hristev2021-01-072-0/+6
| | | | | | | | | | | | | | | | | | Add drivers for flexcom, i2c and eeproms Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | board: atmel: sama7g5ek: add support for MAC address retreivalEugen Hristev2021-01-071-5/+13
| | | | | | | | | | | | | | | | | | | | | Obtain two MAC addresses from the two EEPROMs and configure the two available Ethernet interfaces accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | ARM: dts: sama7g5ek: add i2c1 bus and eepromsEugen Hristev2021-01-071-0/+30
| | | | | | | | | | | | | | | | | | | | | Add node for flx1 i2c1 subnode (and alias to bus 0) This bus has two eeprom devices connected. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-01 20:16:15 +0000